Hi,
Am try ing to figu re out the loc k and hol d ranges and measure the stability of the loop of my attached circuit , I think that I was able to get my phase lock loop locked since the the phase difference as shown in my simulation was clearly constant, but I feel that am missing something here because I could n't see the hol d r ange when I simulated the circuit.
This is a snapshot of the attached circuit:



and here is my initial simulation result:



Again, I wonder what could be the reason for not getting my holding range there.

 

See

 

See
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Thank you Bordodynov for your reply ... once i get off work later tonight , i will go over your change/recommendations and let you know .... Thanks again...

 

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Bordodynov, your recommendation worked perfectly for me and helped me figure out the hold loop and lock loop amazingly. I will keep working on it and try to do more simulation to check its stability and figure out how to make the loop filter faster........... AWESOME ......... Thanks again Bordodynov , I appreciate your help ...............