leaky capacitor effect on oscillator circuit not as expected

Thread Starter

RETIREDTECHNOMAGE

Joined Jun 30, 2018
11
I have a CD4060 oscillator circuit that I need to give a 40 Minute time period from the 14th stage. Historically, I have trimmed the capacitor with smaller caps to get the desired 40 minutes.... typically 1.5 Uf some odd . I then tried trimming the capacitor with a large value resistor ( 300K Ohm ) with the assumption that the resistor would cause a slightly greater discharge rate and thus increase the frequency, which would reduce the resultant time span. In practice, I observe that the OPPOSITE occurs! The frequency is LOWER! I have exploited the anomaly by using a smaller capacitor ( 1 Mf ) and trimming the frequency DOWN to stretch out the time to my wanted 40 minutes. Can anyone explain how a "leaky" capacitor will DECREASE an RC oscillator frequency?
 

Alec_t

Joined Sep 17, 2013
11,285
I think the 'leak' also means that there is less current available to charge up the cap, so it takes longer for the cap voltage to reach the switching threshold of the CMOS gate.
 
Try measure your capacitor value with/without the resistor, you will find it is the same with most multimeters (single ramp) measuring capacitance- they read high value if there is leakage current because some of the charging current is lost in the leakage so it takes longer for the cap to charge.
Also note large X7R ceramic capacitors are terrible for their voltage coefficient of capacitance and they are very non-linear and to be avoided for timing applications.
 

Thread Starter

RETIREDTECHNOMAGE

Joined Jun 30, 2018
11
I appreciate all the replies. It is nice to know that there are still basics to be learned after 60 some odd years. I really had expected the frequency to have increased. I would have failed THAT on a test . My thanks to all who responded.
 

Thread Starter

RETIREDTECHNOMAGE

Joined Jun 30, 2018
11
I think the 'leak' also means that there is less current available to charge up the cap, so it takes longer for the cap voltage to reach the switching threshold of the CMOS gate.
Thank you! I think you hit the nail on the head. I hadn't considered the factors you mentioned....but it makes perfect sense.
 
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