Don't be afraid to fight commonly accepted ideas.

All that can happen is being shunned, at worst, or revered, at best.

I think IEEE should stop acting like Gods'

If I decide that an XOR gate is a bunch of bollocks, then it is.

Love me or hate me.

GOOD COMEBACK, wooo, I thought I was the master of wit.

 

To the best of my knowledge, no formal definition has ever been adopted by a relevant standards body. But decades past the digital logic community informally reached a consensus that a multi-input XOR would behave just like a cascade of 2-input XOR gates since that is the natural interpretation of a sequence of signals in an XOR chain using the shortcut XOR operation symbol. As it turns out, this also happens to behave as an odd-parity detector.

Having looked around, I agree that the general consensus is that an n-input XOR gate behaves as an odd parity generator.

 

If I decide that an XOR gate is a bunch of bollocks, then it is.

You are obviously free to use whatever terminology you want to describe things, except that this type of practices causes great deal of confusion when they don't comply with the widely accepted convention.

This thread is a prime example of that.

 

You are obviously free to use whatever terminology you want to describe things, except that this type of practices causes great deal of confusion when they don't comply with the widely accepted convention.

This thread is a prime example of that.

To be fair, I have seen circuit diagrams where XOR gates with up to 8 inputs are expected to work as a 'one hot' detector, and where one XOR symbol is used, but simply expanded to 8 inputs.
An example comes from fire and gas control for oil rigs. In that case, two or more true inputs represents a fault condition, and the XOR
detects that. A parity generator would fail. How that XOR gate is implemented, depends upon circumstance. Some 'OR' gates are nothing more than 4 or-wired switches, but a mechanical interlock prevents all but one switch being turned -the reason being to force the operator to follow a procedure or for the switches to correspond to graphics on the mimic panel. That switch-bank could be regarded as a 4-input XOR. Perhaps, in that sense, one may implement an n-input XOR gate by whatever means, and call it that. That does not deny there are valid reasons for not doing so.

 

I am pretty sure we are not talking about the same thing. My point is that if you are going to use a common terminology to communicate with others, you better make sure that 1) it means the same to others; or 2) you lay out exactly what you mean. Otherwise, you end up confusing people.

An example comes from fire and gas control for oil rigs. In that case, two or more true inputs represents a fault condition, and the XOR
detects that.

XOR could not have worked in this case - it couldn't have possibly detected the error conditions reliably. OR would, however.

 

I am pretty sure we are not talking about the same thing. My point is that if you are going to use a common terminology to communicate with others, you better make sure that 1) it means the same to others; or 2) you lay out exactly what you mean. Otherwise, you end up confusing people.

This is a key point, though it has been made at least a couple of times in this thread already.

With regards to the multi-input XOR, the takeaway is that while there appears to be widespread consensus on what it means, it is not universal. Thus whenever we see one we would be well-served to take some time and make sure that we understand what that particular use has in mind. On the flip side, as designers we should always make that very clear. Either we should avoid using multi-input XOR gates altogether given that we ARE aware that other people might assume they know what it means and not bother to take the time needed to make sure they understand what WE meant, or we need to document what we mean very clearly at so that it can't be missed, which means right on the schematic where we use it. The former is the better way -- use a custom symbol that reflects the logic function you need.

XOR could not have worked in this case - it couldn't have possibly detected the error conditions reliably. OR would, however.

You are missing his point. He had a logic function that implemented the desired detection function and that function was called, rightly or wrongly, an XOR function.

 

Having looked around, I agree that the general consensus is that an n-input XOR gate behaves as an odd parity generator.

That's the conclusion I came to, though I know that that consensus is not universal.

 

Don't be afraid to fight commonly accepted ideas.

All that can happen is being shunned, at worst, or revered, at best.

Actually, a LOT worse can happen. You can get people killed, for one.

I think IEEE should stop acting like Gods'

They're not.

If I decide that an XOR gate is a bunch of bollocks, then it is.

Okay. Then do so. Of course, if the guy selling you potatoes (or whatever) decides that NIST should stop acting like Gods and decides that a small potato weighs five pounds and then charges you the going rate but uses his definition of the pound, I'm sure you won't have any problem with that.

Or if the pharmacist filling your prescription decides that the people that defined how much a milliliter is didn't know what they were talking about and uses their own definition instead, I'm sure you won't have a problem with that, either.

 

Okay. Then do so. Of course, if the guy selling you potatoes (or whatever) decides that NIST should stop acting like Gods and decides that a small potato weighs five pounds and then charges you the going rate but uses his definition of the pound, I'm sure you won't have any problem with that.

Or if the pharmacist filling your prescription decides that the people that defined how much a milliliter is didn't know what they were talking about and uses their own definition instead, I'm sure you won't have a problem with that, either.

Two elegant ways of saying "go F yourself". I can't believe how patiently you argue semantics with these guys.

 

I am pretty sure we are not talking about the same thing. My point is that if you are going to use a common terminology to communicate with others, you better make sure that 1) it means the same to others; or 2) you lay out exactly what you mean. Otherwise, you end up confusing people.



XOR could not have worked in this case - it couldn't have possibly detected the error conditions reliably. OR would, however.

The schematics in question are reviewed and authorised by chartered engineering groups, representing insurance companies.
There is a catalogue extending 30 years, so I expect change would cause a lot of confusion.
XOR works in the given case, because if there are no true inputs, the output is false, indicating an error condition. Cable torn away, power supply dead. Two or more true inputs is also an error condition. OR would not satisfy the last requirement. Some may think they have the authority to determine what is correct, perhaps because they have not been exposed to situations that show they don't.

 

"OR would not satisfy the last requirement"

Really?

In your world, 1 OR 1 OR 0 = ? And 1 XOR 1 XOR 0 = ?

Also, 1 OR 0 OR 0 = ? And 1 XOR 0 XOR 0 = ?

If you are unsure, run them through a computer.

 

"OR would not satisfy the last requirement"

Really?

In your world, 1 OR 1 OR 0 = ? And 1 XOR 1 XOR 0 = ?

Also, 1 OR 0 OR 0 = ? And 1 XOR 0 XOR 0 = ?

If you are unsure, run them through a computer.

You are making the mistake of assuming that A XOR B XOR C defines a three-input XOR function. But that is NOT the definition of the XOR function that the schematics he is referring to are using. That definition, which is quite defensible, is that the output is HI if and only if exactly one of the inputs is HI, also known as a "one-hot detector". This is very, very different from an odd-parity detector.

 

Two elegant ways of saying "go F yourself". I can't believe how patiently you argue semantics with these guys.

Indeed, sometimes I wonder if our friend has Vulcan genes in him...

 

Hi,

Wow lots of relies since my last check. My "Alerts" do not always work for some reason so i miss some threads that have been replied to.

But back to the topic...

WBahn had said, to paraphrase, that he had said all along that the XOR gate with more than two inputs should not be defined as an XOR gate at all. I ended up coming to the same conclusion now.

The topic then shifted a little to what exactly is considered basic logic and what is considered combinational logic. The conclusion is that even the two input XOR gate is combinational logic.

Logic is a very interesting topic because of the simplifications that appear due to the fact that there are only two allowed states, true or false usually denoted by "1" and "0" respectively, whereas almost everything else in mathematics and electrical engineering requires variables that have range minus infinity to plus infinity and can take on infinitesimally small values near 1/(-infinity) or 1/(+infinity). So the range in other areas is almost unlimited (some simplifications do occur even because of the plus and minus infinity) but with logic it is so limited that things come up that are often almost shocking because we are so used to thinking in terms of regular algebra with values with unlimited ranges.

One of the most interesting ideas, if i remember this right, is that of the single inverter logic circuit.
The question is, what can you make with an unlimited number of AND and OR gates, and just ONE inverter gate?
The answer is, ANY LOGIC CIRCUIT that has ever been made or ever will be made with two state logic.
I'll have to look this up again because i cant remember if it was an infinite logic circuit or just a really big logic circuit, but i think it was any logic circuit. This implies a huge logic circuit with immensely complex function, an example would be a totally combinational chess solver circuit, that could play all the possible combinations of the game of chess with just pure logic and no flip flops, which means the time it takes to get from the start of any game to the end would be perhaps just tens of nanoseconds.
There was a good example in an automated reasoning (like artificial intelligence) book i read a long time ago, but i'll have to look for that again some time. It's a big circuit though anyway so it's hard to draw out.

What this tells me is that the low level logic is just AND, OR, and NOT. And if you allow more than one NOT gate then it's easier to make OR from AND or AND from OR. In fact, you can make OR from AND and three NOT gates as we all probably know already:
a+b=(a'*b')'

and vice versa.

 

One of the most interesting ideas, if i remember this right, is that of the single inverter logic circuit.
The question is, what can you make with an unlimited number of AND and OR gates, and just ONE inverter gate?
The answer is, ANY LOGIC CIRCUIT that has ever been made or ever will be made with two state logic.

I don't buy this. If nothing else, logic circuits can have multiple outputs some of which are inverted.

Let's pick a simple one to start with -- a 2-to-4 decoder. How can that be implemented using only ANDs and ORs plus no more than one inverter?

 

y = ((a ^ b) ^ c) ^ (a & b & c)

A generic form of it would be:

y = XOR(x1, x2, ..., xi) XOR AND (x1, x2, ..., xi).

y = 1 if any of the following is true:

1. XOR(x1, x2, ..., xi) = 1, and AND (x1, x2, ..., xi) = 0: ie, odd number of xi is 1 and at least one xi is 0;
2. XOR(x1, x2, ..., xi) = 0, and AND (x1, x2, ..., xi) = 1: ie, even number of xi is 1 and all xi is 1.

Condition #2 can only exist for even number of all 1 inputs.
Condition #1 detects odd number of 1 inputs when at least some of the inputs are 0 -> an odd number of ***all*** 1 inputs will yield a 0, not surprisingly.

Hope it helps.

 

I don't buy this. If nothing else, logic circuits can have multiple outputs some of which are inverted.

Let's pick a simple one to start with -- a 2-to-4 decoder. How can that be implemented using only ANDs and ORs plus no more than one inverter?

Hello again WBahn,

My alerts worked today so i was able to see this reply right away.

I am happy you brought this question up. Unfortunately, i do not remember that much about this. That means there could be a certain requirement for the circuit under consideration. I'll have to try to think about this and see what i can remember. I would like to refresh on this subject too.

In the mean time, would you be happy enough with a small but still interesting alternate example of another circuit? This one is almost as interesting as trying to use just one inverter for a circuit. I will warn however that my memory is not as good as it used to be

The new circuit challenge:
We have a three input logic circuit, with three outputs. We want ALL THREE inputs to be inverted. The challenge is to use JUST TWO inverters, not three as we would normally jump into.
To rephrase a little, we have three separate inputs A,B,C, and three separate outputs D,E,F, and the output expressions must be:
D=A'
E=B'
F=C'

and there are no tricks here (such as some info left out that would solve the problem in a jiffy).

Would you settle for that at least for now? I think i can remember how to do this one.

 

The question is, what can you make with an unlimited number of AND and OR gates, and just ONE inverter gate?

This is not really what I have been saying.

I think that theoretically, all logic circuits can be made from NOT gates and AND gates, or NOT gates and OR gates, because each is a fundamental logic unit.
For instance, take an AND (or OR) gate with TWO inputs and ONE output, and a NOT gate with ONE input and ONE output (a two input NOT gate is nonsensical).
The reason that these gates are fundamental is that from the four combinations of input 00, 01, 10 and 11, there is only ONE unique output, either 0, 0, 0, 1 for AND, or 0, 1, 1, 1 for OR.
XOR is not fundamental because it has two outcomes for four combinations of input, 0, 1, 1, 0 in this case.

Now, a THREE input AND (or OR) gate also has ONE unique outcome from EIGHT combinations of input. That is, 1 for an input 111, and a 0 for all other inputs 000, 001, 010, 011, 100, 101 and 110 (in binary notation, and inputs A, B and C are in any order).
The reason that a THREE input AND gate seems to be a logical extension of a TWO input AND gate is that:
1/ It still has one unique output, and:
2/ It still follows our basic concept of an AND function.

I would't say it was FUNDAMENTAL though, because it can be made from two, TWO input AND gates.

What makes AND and OR and NOT useful, is that each in combination can describe the four unique outcomes of a TWO input gate.
That is, for TWO inputs of 00, 01, 10, 11, in any order: OR gives 0, 1, 1, 1: AND gives 0, 0, 0, 1: NOR gives 1, 0, 0, 0: NAND gives 1, 0, 0, 0.

This makes it intuitive when designing simple logic. And there will always be a place in circuit design where a handful of gates will do a better job than a Micro Control Unit or a Large Scale Integration (LSI) Gate Array.

Now, we can choose, If We Like, to reduce this combination of OR, AND, NOR and NAND down to a SINGLE FUNDAMENTAL UNIT, say, for instance, a NAND gate, because, ultimately, all other logic can be made from this, including an XOR gate.
You cannot make a NAND gate for XOR gates (and if someone can, I would be interested to know).
This in theory only, and agree that the IEEE stand OR, AND and NOT clarify there functions to the point of saving lives.

Practically though, and correct me if I'm wrong, but don't manufactures of LSI devices in some cases use ONLY NAND gates on there silicon real-estate. N-channel MOSFET's are faster than P-channel (because the current mechanism uses electron flow rather than hole flow), they are simpler to populate using current methods, resistors are made from them, they inherently follow NAND and NOT in there optimal circuit configuration, and because ONLY NAND's are used, complexity is minimized.

To sum up:
Yes, it is useful to have a universal definition of NOT, OR, AND and XOR, but
No, you cannot intuitively scale XOR to three or more inputs like AND and OR.

I hope I have confused the thread

 

NAND gives 1, 0, 0, 0

Sorry, NAND gives 1, 1, 1, 0