http://www.waferfabs.org/?q=node/2381

 

The ultimate Maker Space. Fabbing micro chips?

 

Pretty close, I've got a few 'first' silicon die on new devices including a few first fab production wafers as souvenirs.

 

Would hobbyist be interested in custom silicon chips?

 

Would hobbyist be interested in custom silicon chips?

Sure, there's a few places to have your own design rolled if you have a deep bankroll.

You can make simple chips at home.
http://www.josepino.com/diy/making-homemade-transistors

20+ years ago we were still using a lot of liquid phase epitaxy for doping but today even diffusion is being replaced by ion beam processes to get the needed process precision.

 

With the advent of FPGA/CPLD and other PSOC products, why would the hobbist bother with fab? He can make his own custom IC"s at home.

 

Package maybe? Analogue signals perhaps? Complete control over the design and does not have to be synchronous (unlike FPGA where you should use a synced design instead of an aysnc but that has never stopped me before).

Personally if I had the choice of either an FPGA in a BGA package or TSOP against a custom silicon chip in DIP or SOIC I would go silicon hands down. Personally have had a bit of experience in silicon design so I am happy with the transistor sizing/layout etc..

 

does not have to be synchronous

FPGA's don't care about that.

Personally if I had the choice of either an FPGA in a BGA package or TSOP against a custom silicon chip in DIP or SOIC I would go silicon hands down.

http://www.mouser.com/ProductDetail/Atmel/ATF750LVC-15SU/?qs=b1J4i6otjZuGI1NPYNxERg==&gclid=CjwKEAjws7OwBRCn2Ome5tPP8gESJAAfopWsGT6Ga0xb-OR147iDccXjA44jvEW-wvk7Xhw2wQMx3RoCXx7w_wcB&kpid=55894416

 

10 Macrocells, great...

I designed and created (fully working), composite video graphics card that needed two Xilinx 95XL72 CPLDs in PLCC packaging (total of 144 macrocells). And even then I needed external IO control via 7400 chips. It would have been great to have the whole thing on a single chip (micro's are not fast enough nor have enough memory).

FPGAs and CPLD both do not care about design being sync/ async BUT you have race condittions and because you do not know how the routing is done you cannot time your signals (hence why async is not advised in FPGA design). In silicon you can carefully trim and design your metal layers so that signals arrive before other signals do. For example, pulse creation on a flip flop clock or latched device is done using carefully designed silicon.

 

10 Macrocells, great...

I designed and created (fully working), composite video graphics card that needed two Xilinx 95XL72 CPLDs in PLCC packaging (total of 144 macrocells). And even then I needed external IO control via 7400 chips. It would have been great to have the whole thing on a single chip

The why didn't you?

FPGAs and CPLD both do not care about design being sync/ async BUT you have race condittions and because you do not know how the routing is done you cannot time your signals (hence why async is not advised in FPGA design). In silicon you can carefully trim and design your metal layers so that signals arrive before other signals do. For example, pulse creation on a flip flop clock or latched device is done using carefully designed silicon.

You can do all that with FPGA's too. It's a matter of secifying constraints.

 

I cant have the whole design on a single chip because I cant afford to get a chip fabricated. And the only devices which have enough IO + cells are BGAs which require re-flowing and it just gets out of hand. Plus if there is a mistake then you need to get an other PCB which is pricey.

I know that you can specify constraints but every tutorial, lesson or advice from senior engineers who have experience in FPGA design all agree that async designs are bad and must be avoided.

 

I cant have the whole design on a single chip because I cant afford to get a chip fabricated. ... Plus if there is a mistake then you need to get an other PCB which is pricey.

That was the point I was trying to make. Unless you're a well-funded manufacturer, programmable devices are the way to go. They aren't perfect; slower, less dense, etc. But for homebrew, they are just about the only viable choice.

I know that you can specify constraints but every tutorial, lesson or advice from senior engineers who have experience in FPGA design all agree that async designs are bad and must be avoided.

That's pretty much the path for all digital design going forward.[/QUOTE][/QUOTE]

 

Talking about FABs, it's a complex machine that doesn't like to stop but sometimes you have the pleasure of pressing the big RED off button.

From a public report.

Steve Sanghi - CEO
Well, let me comment on the utilization. First of all, the Gresham factory in Oregon is a newer factory and in a newer factory we need a -- once in a five years we need a major shutdown to repair things that can't be repaired while the factory is running. And that shut down has been previously scheduled for a year for this October and that shutdown usually is about seven to eight days you have to shut the factory and we reserve for it going into that shutdown, and it's planned shutdown, we have to do it every once in a five years.