i need help to build my first circuit !

Thread Starter

bright22

Joined Feb 23, 2015
9
hello every one

i'm totally new to the computer organization and circuits ,, i really wish you can help me with my first project .. so the project is :
1. Build and test a simple RS latch (use two NOR gates for the implementation).
2. Build and test an RS master slave flip-flop. It should use two of your simple RS latches and it must include a clock signal.

3. Build and test the one bit memory as it was desgined in class. Start with your RS master-slave flip-flop.

and then include all three circuits in one Logisim (.circ) document.
Make circuit number 3 (the one bit memory) the "main" circuit.

what i can do for now is #1 which is i built the RS latch i used two nor gates ,,
how can i solve the others ? do i need to build another circuit ? or i should use the first ?

please help me i'm really lost here..
thank you ..

bright !
 

Thread Starter

bright22

Joined Feb 23, 2015
9
I have no idea what your "main circuit" is supposed to do. What, exactly, is your assignment?
1. Build and test a simple RS latch (use two NOR gates for the implementation).
2. Build and test an RS master slave flip-flop. It should use two of your simple RS latches and it must include a clock signal.

3. Build and test the one bit memory as it was desgined in class. Start with your RS master-slave flip-flop.

and then include all three circuits in one Logisim (.circ) document.
Make circuit number 3 (the one bit memory) the "main" circuit.



this is my assignment
 

WBahn

Joined Mar 31, 2012
25,217
I'm assuming (and could well be wrong) that you are supposed to design a one bit memory that, as part of it, instantiates an RS MSFF which, in turn, instantiates an RS FF. If I'm correct, then the memory implementation you show in Post #5 won't cut it because you are using a subcircuit (the FF block) that you haven't built (unless that is supposed to be your RS MSFF, but I don't see anything that indicates that that's the case.

Not being familiar with LogiSim, I don't know how it organizes circuits. Most schematic capture tools have a separate file for each schematic and usually a separate file for each symbol. You create a simple that you can place in one schematic that instantiates one occurrence of the associated schematic. When you netlist the top-level schematic, it creates a SPICE netlist (of some flavor) that contains all of the subcircuits from all of the schematics that were instantiated in either the top-level schematic or any of its children. Does that make sense given what you know about LogiSim?
 
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