Here's a circuit that uses 4 positive-edge JK flip flops and an AND gate to output 9 unique sequential states. The AND gate provides the reset logic to reset the flip-flops when the counter reaches 1001 (10 in binary). Next comes the decoder logic to light the relevant segments but you mentioned you know how to do that.

Using this circuit as a reference, can you figure out how to design a truth table and state diagram including the clock, reset and AND gate?

View attachment 338611

Click this link to launch the simulator.

https://tinyurl.com/2ah4s8nz

Hi again sir,

I have already create simulation a 4-bit up-counter using JK with proteus.
Here is the simulation jpg
Thanks again

 

Hi Sir @Art Vandelay
I'm really appreciate that you are taking time for me. Thanks again.
So i have fill the table and write a python code using pandas library for good visualization
Is there any mistake ?
Thanks

The table looks good but I can't make sense of the data. Here's the truth table I came up with for my circuit in post #19.



For a combinational logic circuit, only 1 row of this table can be true (or in effect) at any given time called the state (ignoring transmission time etc.). In my table, each state is characterized by the values of the inputs and outputs as they are at that time.

Think of it like this, and you can verify the state transitions by watching my simulation at low speed.

a) The machine starts at State 0. Sample the voltages at each input and output and record in the table: 0000 1111 0
b) Clock pulse. Machine changes to State 1. Sample the voltages at each input and output and record in the table: 0001 1111 0
c) Clock pulse. Machine changes to State 2. Sample the voltages at each input and output and record in the table: 0010 1111 0

Keep in mind the change from State 9 to 0 happens "instantly" but there are 10 states in total.

 

@Art Vandelay

Sir sorry but i just cant understand. How did you create this table without using Q+(Next state) ? What is my next state for our sequence ? I'm really sorry for being dumb but i cant just understand. Please can you provide me more details ?

 

I have already create simulation a 4-bit up-counter using JK with proteus.
Here is the simulation jpg

Why are you using an asynchronous counter?

 

@Art Vandelay

Sir sorry but i just cant understand. How did you create this table without using Q+(Next state) ? What is my next state for our sequence ? I'm really sorry for being dumb but i cant just understand. Please can you provide me more details ?

Q+ (n+1, n+2) is implied in my table along with ¬Q since J and K are always 1 (toggle). I made an error earlier when I said Q+ should always be the opposite of Q. I was referring to ¬Q when I said that.

In plain terms, Q will become Q+ on the next clock pulse and ¬Q is the opposite of Q. Here's the the first 4 rows with Q+ and ¬Q added in the form Q4, Q3, Q2, Q1, ¬Q4, ¬Q3, ¬Q2, ¬Q1, Q+4, Q+3, Q+2, Q+1

0000 1111 0001
0001 1110 0010
0010 1101 0011
0011 1100 0100

Now this shows the current state of Q and ¬Q. It also predicts what Q will be on the next clock pulse (Q+1). Do you see the pattern between Q and Q+?

 

Why are you using an asynchronous counter?

Hi Sir @dl324
I just want to do a up/down counter. So i decided to do a asynchronous counter. If i want to follow desired sequence from my circuit, should i use Synchronous Counter ?

 

If i want to follow desired sequence from my circuit, should i use Synchronous Counter ?

You wouldn't have to contend with glitches if you used a synchronous counter.

 

Hi Sir @dl324
I just want to do a up/down counter. So i decided to do a asynchronous counter. If i want to follow desired sequence from my circuit, should i use Synchronous Counter ?

My strong recommendation is to use fully-synchronous logic unless you have a damn good reason to go asynchronous (and there are plenty of damn good reasons out there). If you opt to go asynchronous, then you implicitly accept the responsibility to expend all of the design effort to identify and content all of the demons that roam those waters.