Given the NMOS model below from the Keysight ADS.
How do I decrease the Ron (On resistance) with given NMOS parameters, of course without changing the geometry of the NMOSFET (width and length)

 

When the geometry (length, width) is fixed, the only parameter remaining is the gate voltage: higher gate voltage -> lower Ron. Within the limits the oxide thickness allows.

 

When the geometry (length, width) is fixed, the only parameter remaining is the gate voltage: higher gate voltage -> lower Ron. Within the limits the oxide thickness allows.

It is common for the increase in gate voltage to have a negligible effect past a certain level. If the absolute maximum Vgs is say +20 VDC, it would not surprise me to see the minimum rds(on) at about +10 VDC. Increasing Vgs past this point would be pointless.

 

Beyond Vgs = 10 V, the decrease of RDSon is not much, but it's still decreasing.
Just one example: https://www.onsemi.com/pdf/datasheet/nds7002a-d.pdf