How to decrease the Ron (On resistance) with given NMOS parameters

Thread Starter

achen

Joined Sep 11, 2022
18
Given the NMOS model below from the Keysight ADS.
How do I decrease the Ron (On resistance) with given NMOS parameters, of course without changing the geometry of the NMOSFET (width and length)
1664938190732.png
 

du00000001

Joined Nov 10, 2020
113
When the geometry (length, width) is fixed, the only parameter remaining is the gate voltage: higher gate voltage -> lower Ron. Within the limits the oxide thickness allows.
 

Papabravo

Joined Feb 24, 2006
19,595
When the geometry (length, width) is fixed, the only parameter remaining is the gate voltage: higher gate voltage -> lower Ron. Within the limits the oxide thickness allows.
It is common for the increase in gate voltage to have a negligible effect past a certain level. If the absolute maximum Vgs is say +20 VDC, it would not surprise me to see the minimum rds(on) at about +10 VDC. Increasing Vgs past this point would be pointless.
 
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