Hello,

I have a problem with logic of case statement in vhdl. I wonder if the variable that selects the case condition can be changed within the statement. To clarify:

process(clk) 

variable aaa: std_logic_vector(2 downto 0):="000"; 

case  aaa  is 

    when  "000"  => 
      if () then 
        something 
      end if; 
      aaa := aaa+1; 

    when  "001" => 
        if() then
      something 
        elsif() then
        something
         else
         something
       end if;
      aaa := aaa+1; 

    when others => 
      -- sequential statements 


end   case ; 

end process;

When I tried to synthesize a code with that algorithm, it displays an error. What is the problem here? Can't I change the variable within the case? Or the problem is about the if statements in the case? I know that it looks like a pl code instead of a HDL code, but I'm used to pl's, and getting started to VHDL

 

...it displays an error. What is the problem here?

We are no oracles, so unless you post the exact wording of the error I doubt that we can be of much help. I currently don't have the development suite running, so I cant try the code for myself.

 

PROCESS (h_position, v_position)
variable cnt : std_logic_vector(3 downto 0 ):="0000";
variable decimalcnt: std_logic_vector(3 downto 0):="0000";
BEGIN 
IF ((hareketsiz_hedef > "000") AND (h_position >= YK4) AND (h_position < YK4+YB4) AND (v_position >= DK4) AND (v_position < DK4+DB4)) THEN
y <= GS4 & "00"; 
cr <= CR4 & "00"; 
cb <= CB4 & "00"; 
ELSIF ((hareketsiz_hedef > "001") AND (h_position >= YK5) AND (h_position < YK5+YB5) AND (v_position >= DK5) AND (v_position < DK5+DB5)) THEN
y <= GS5 & "00"; 
cr <= CR5 & "00"; 
cb <= CB5 & "00"; 
ELSE 
if ( f='1') then
case1: CASE cnt IS
WHEN "0000" =>
IF ((hareketsiz_hedef > "000") AND (h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR 
((hareketsiz_hedef > "000")AND (h_position >= "1010001010") AND (h_position < "1010001100") AND (v_position >= "0110100110") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND (h_position >= "1010010010") AND (h_position < "1010010100") AND (v_position >= "0110100110") AND (v_position < "0110101110"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
ELSIF((hareketsiz_hedef > "000") AND(h_position >= "1010001100") AND (h_position < "1010010010") AND (v_position >= "0110100100") AND (v_position < "0110101100")) THEN
y <= "1110101100"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
cnt := cnt +1;
WHEN "0001" =>
IF((hareketsiz_hedef > "000") AND(h_position >= "1010010010") AND (h_position < "1010010100") AND (v_position >= "0110100110") AND (v_position < "0110101110"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
cnt := cnt +1;
WHEN "0010" =>
IF ( (hareketsiz_hedef > "000")AND (h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR 
((hareketsiz_hedef > "000") AND (h_position >= "1010001010") AND (h_position < "1010001100") AND (v_position >= "0110101010") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND(h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1010010010") AND (h_position < "1010010100") AND (v_position >= "0110100110") AND (v_position < "0110101010")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1010001010") AND (h_position < "1010010100") AND (v_position >= "0110101000") AND (v_position < "0110101010"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
cnt :=cnt+1;
WHEN others => null;
END CASE;
case2: CASE decimalcnt IS
WHEN "0000" =>
IF ((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR 
((hareketsiz_hedef > "000")AND (h_position >= "1001111011") AND (h_position < "1001111101") AND (v_position >= "0110100111") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1010000011") AND (h_position < "1010000101") AND (v_position >= "0110100111") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101100") AND (v_position < "0110101110"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
ELSIF((hareketsiz_hedef > "000")AND(h_position >= "1001111101") AND (h_position < "1010000011") AND (v_position >= "0110100100") AND (v_position < "0110101100")) THEN
y <= "1110101100"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
WHEN "0001" =>
IF ((hareketsiz_hedef > "000")AND(h_position >= "1010000011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110101110"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
WHEN "0010" =>
IF ( (hareketsiz_hedef > "000")AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR 
((hareketsiz_hedef > "000") AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101010") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000")AND (h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100110") AND (v_position < "0110101010")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101000") AND (v_position < "0110101010"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
WHEN "0011" =>
IF ((hareketsiz_hedef > "000")AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100100") AND (v_position < "0110100110")) OR 
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101100") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110100110") AND (v_position < "0110101110")) OR
((hareketsiz_hedef > "000") AND(h_position >= "1001111011") AND (h_position < "1010000101") AND (v_position >= "0110101000") AND (v_position < "0110101010"))THEN
y <= "0001000000"; 
cr <= "1000000000"; 
cb <= "1000000000";
END IF;
WHEN others =>
null; END CASE; end if; 
END IF;END PROCESS;

 

the code is too long to inspect, I'm sorry about that. Now I got rid of the error, code is implemented on fpga but I still have a problem. This is a video maker code and the aim is creating a counter on the screen. Variable "cnt" and "decimalcnt"should update on the screen but now, I only see a "0" which corresponds to where "decimalcnt" should appear. And "cnt" is not seen at all. However, "cnt" should have count from 0 to 2. I hope I could clarify the problem little bit.

 

I think you need Libary unsigned and use unsigned.all in order to increment the std_logic_vector.