Please help me on this..

The following circuit is a power amplifier with output current limiting provided by transistors Q4 and Q5 .The voltage drop across RB2 and RB3 produced by IL(load current) will turn Q4 and Q5 ‘ON’.


Now the thing which i am not getting is that the text says that the transistors Q4 and Q5 will get ‘ON’ only when IL is selected at IL (max) level.

But any transistor will get ‘ON’ only by a meagre amount of 0.6 V which is far lower than the voltage drop (VRB2 and VRB3) which is caused when IL is maximum.


So how can the text says that the transistors will get ‘ON’ only by the voltage drop caused when IL is at maximum level ??

thanks..

 

Well ILmax = VbeQ4/Rb2

And this circuit work exactly the same as this circuit
http://forum.allaboutcircuits.com/threads/regulated-power-supplies-current-limiting.113281/

 

hi,
The quiescent bias for Q2 and Q3 is created by the voltage drop across D1, D2 and the Rb variable.
This bias is just enough to set Q2 and Q3 into conduction, this form of biasing is required to prevent cross over distortion as the two transistors alternately conduct.

RA2 and RB2 are in the Emitter of Q2 and form a potential divider whose voltage output is determined by the current thru Q2.

If the Q2 current reaches the desired maximum level, the voltage at the divider junction is sufficient to turn on Q5, this causes a reduction in the bias voltage due to D1,D2, Rb and so limits the Q2 current to the desired maximum permitted level.

The same action applies to the lower Q3 transistor network.

Do you follow that OK.?
E

EDIT:
I should point out that the maximum permitted current level only occurs at the peak current swings in Q2 and Q2 when being driven by the input signal, usually an audio signal.

The current limiting 'clips' [limits] the peak excursion of the Q2 or Q3 currents so keeping the the transistors within their specified maximum current limit.

 

Ok... IL max would be that current value at which transistor Q4 turns 'ON'.

And If we want to increase the limiting current range do we have to decrease the value of RB2..???

am i right??

 

hi,
If the Q2 current reaches the desired maximum level, the voltage at the divider junction is sufficient to turn on Q5 (Q4), this causes a reduction in the bias voltage due to D1,D2, Rb and so limits the Q2 current to the desired maximum permitted level.

Are you sure that D1,D2, Rb has any think to do with "current limiting"?
And this circuit will work as expected only if "driver" current (the source for Q2 current) is limited in some way because ILmax = IQ2 + IQ4.

 

Are you sure that D1,D2, Rb has any think to do with "current limiting"?

Are you sure that it doesn't.?
After all the signal drive voltage is applied across D1,D2 and Rb and it is the action of Q4 and Q5 which limit the voltage across D1, D2 and Rb.
So D1, D2 and Rb are an integral part of the limiting.

I said.

The quiescent bias for Q2 and Q3 is created by the voltage drop across D1, D2 and the Rb variable.
This bias is just enough to set Q2 and Q3 into conduction, this form of biasing is required to prevent cross over distortion as the two transistors alternately conduct.

Also.

If the Q2 current reaches the desired maximum level, the voltage at the divider junction is sufficient to turn on Q5, this causes a reduction in the bias voltage due to D1,D2, Rb and so limits the Q2 current to the desired maximum permitted level.

The audio input signal is applied across D1,D2 and Rb
So,
Perhaps I should have said,
this causes a reduction in the voltage across D1,D2, Rb and so limits the Q2 current to the desired maximum permitted level.

I expect the TS to know what I meant.

E

 

Are you sure that D1,D2, Rb has any think to do with "current limiting"?
And this circuit will work as expected only if "driver" current (the source for Q2 current) is limited in some way because ILmax = IQ2 + IQ4.

Eric was saying that the bias voltage is caused - supplied, or created - by D1, etc., not that the bias voltage affects current limiting.

And you statement about ILmax is correct, but it doesn't show that IQ4 is actually current intended for Q2base stolen away by Q4. That is he limiting action.

Note that the circuit will not work unless there are resistors or other current source/sink means between Q2 and Q3 bases and collectors.

ak

 

And If we want to increase the limiting current range do we have to decrease the value of RB2..??? am i right??

Do you mean increase the level at which current limiting occurs.?
If Yes, you are right.

 

his causes a reduction in the bias voltage due to D1,D2, Rb and so limits the Q2 current to the desired maximum permitted level.

what i probably think is its not D1,D2 and Rb that causes reduction in the bias voltage ...as the Q2 current reaches maximum level Q4 gets ON
which pulls the base of Q2 down so that Q2 cannot provide current in excess of IL max..and this means the same which Jony130 told in post #5.

however the role of D1 and D2 is just to bias the output transistors in order to eliminate crossover distortion by supplying dc voltage at the output for a period of 1.4 V base voltage swing...which in otherwise would have been zero(output voltage) in absence of any biasing network....also diode provide temparature compensation also ..but the main consideration should be that these diodes should be thermally matched with the transistors and should share the same heat sinks of the output transistors............other than Rb is there to adjust this dc offset ..
The extent and how this dc offset effects the audio output quality is out of my knowledge...

 

please elaborate...


".... that the circuit will not work unless there are resistors or other current source/sink means between Q2 and Q3 bases and collectors."

 

Do you mean increase the level at which current limiting occurs.?
If Yes, you are right.

By current limiting range i mean that more current flow through the output transistors followed by limiting action of Q4..thus if the value of RB2 decreases more current will flow across it in order to create a voltage drop that could turn the transistor Q4 ON..hence current handling range is improved.

 

what i probably think is its not D1,D2 and Rb that causes reduction in the bias voltage

I never said it was.

I said:

this causes a reduction in the voltage across D1,D2, Rb and so limits the Q2 current to the desired maximum permitted level.

which is the same as you said, but in different words.

what i probably think is its not D1,D2 and Rb that causes reduction in the bias voltage ...as the Q2 current reaches maximum level Q4 gets ON
which pulls the base of Q2 down so that Q2 cannot provide current in excess of IL max..and this means the same which Jony130 told in post #5.

 

By current limiting range i mean that more current flow through the output transistors followed by limiting action of Q4..thus if the value of RB2 decreases more current will flow across it in order to create a voltage drop that could turn the transistor Q4 ON..hence current handling range is improved.

This should read:
if the value of RB2 decreases, more current will have to flow thru it in order to create the same voltage drop that would start to turn the transistor Q4 ON.

It is not a case of if Q4 is either On or Off, its is not acting as a switch, the greater the current thru Q2 , harder Q2 conducts.
If you scoped a sine wave output signal waveform, the top of the wave, during current limiting, would not be flat, but partially rounded.

Exactly what are you trying to do with your amplifiers output stage.?

E

 

I never said it was.

I said:


which is the same as you said, but in different words.

Sorry i didn't corelated it that way..
as D1,Rb ,D2 and Q4 ,Q5 is a parrallel combination..hence any change in Q4 ,Q5 voltage will inflicted the same change in the voltage levels of the diodes..

 

If you scoped a sine wave output signal waveform, the top of the wave, during current limiting, would not be flat, but partially rounded.

maybe the output signal is rounded because of the storage time (turn off time) of the transistor..???

 

maybe the output signal is rounded because of the storage time (turn off time) of the transistor.

No,
Its due to the Q2 transistor working in its linear range.

 

I am not correctly able to visualize the working of catch diodes show in the figure when inductive load is considered..most probably they are there to counter the back emf generated by inductive load...are they been there to sink current towards the ground??
..if yes then why the above catch diode heading towards Vcc..

please help me guys...

 

If the voltage swing at the output exceeds the power supply voltage levels, which could happen with an inductive load, the top diode clamps the Vout to +Vsupply +0.7v
Or if a negative going transient which exceeds -Vsupply the lower diode clamps the Vout

Do you follow that OK.?

 

You didn't compress the image and also used the wrong format to save the image, too much file size will affecting the connection speed for the forum, and it is unnecessary, I already compressed it from about 1.9MB reduced to 50KB and also modified the file format from png to jpg.

 

I am not correctly able to visualize the working of catch diodes show in the figure when inductive load is considered..most probably they are there to counter the back emf generated by inductive load...are they been there to sink current towards the ground??

Snubber diodes clamp the kickback to the supplies when an inductive load is switched. This is done to protect the switch.

When MOSFET drivers are used, some have sufficient built-in protection and don't need an external snubber.

PS - thanks for changing your avatar. It kept reminding me of a guy who used to be a politician in some country; and I'd prefer to forget about him...