Guys, Please help me out to get an answer for my question,

How the hardware designer determined the suitable frequency of the clock for his device to work on ? After which he created the timing diagram which is then further used for interfacing.

All I need to know what is the mechanism for determining the suitable clock and then creating the timing diagrams. My own logic is first designer creates the device such as Microprocessor then give it different instructions and then check the results on different clock rates but this is hit and trial method is there any specific algorithm to do that ?

 

Guys, Please help me out to get an answer for my question,

How the hardware designer determined the suitable frequency of the clock for his device to work on ? After which he created the timing diagram which is then further used for interfacing.

All I need to know what is the mechanism for determining the suitable clock and then creating the timing diagrams. My own logic is first designer creates the device such as Microprocessor then give it different instructions and then check the results on different clock rates but this is hit and trial method is there any specific algorithm to do that ?

The capacitance of the inputs, the propagation delay, the rise time of the output.

The drive current of the inputs, the capacitance and drive current of the output. Technology tests of all of these (and more) allow incremental steps of improvement.

 

The eye pattern test can provide indications when speed limits have been reached. The test engineer can then log error rates versus frequency.

 

You generally start with a specification -- you need a system to achieve a certain level of performance in order to meet your customers' needs. You then design a system that performs the needed tasks and, as part of that, you determine what the critical path is that dictates what the minimum clock speed is that will let the system perform those tasks in the time that is required. With that you are in a position to determine the maximum delay the various components can tolerate and, once you have that, you can design those components to, hopefully, achieve those requirements by designing the gates and interconnects with a variety of factors, including parasitic capacitances from all sorts of sources, and simulating the circuits to ensure that they will actually do so over the range of parameters (such as temperature and process variation) that you are interested in.

 

You generally start with a specification -- you need a system to achieve a certain level of performance in order to meet your customers' needs. You then design a system that performs the needed tasks and, as part of that, you determine what the critical path is that dictates what the minimum clock speed is that will let the system perform those tasks in the time that is required. With that you are in a position to determine the maximum delay the various components can tolerate and, once you have that, you can design those components to, hopefully, achieve those requirements by designing the gates and interconnects with a variety of factors, including parasitic capacitances from all sorts of sources, and simulating the circuits to ensure that they will actually do so over the range of parameters (such as temperature and process variation) that you are interested in.

Ok we can identify the critical paths and for some logic design also we need to know the time delay due to the wires and other stuff, How can we do that ?

MOD EDIT: Correct QUOTE tags

 

Ok we can identify the critical paths and for some logic design also we need to know the time delay due to the wires and other stuff, How can we do that ?

MOD EDIT: Correct QUOTE tags

Via modeling and simulation. Depending on how critical accurate values are, we can analyze the tracks connecting components in order to determine the parasitic resistances and capacitances as well as the coupling coefficients to nearby tracks, power planes, and the substrate and even electromagnetic coupling. We can also take into account the effects of the areas and perimeters of source-drain regions and many other things. In practice, you want to take into account only those things that are important in each part of the circuit. The parameter values are generally tabulated in the process design documents and also built into the device models provided by the fab house who very carefully determined those parameters via actual measurement of test structures actually fabricated on the wafers.