Hi, can somebody show me how to design a comparator with a gain that is larger than 100000? The one I have now has the gain about 2000 which is not good enough. The comparator I have now consists 3 stages: the differential amplifier with active loads, hysteresis, and a complementary CMOS differential amplifier. I tried to add gain stage, which is a common-gate configuration. But that is still not good enough. Therefore, I think I need to try a different type of architecture.
Finally, Can someone recommend some A/D books to me? So far, I have "Principles of Data Conversion System Design" by Razavi and "CMOS Circuit Design, Layout and Simulation" by Baker, Li and Boyce.
Finally, Can someone recommend some A/D books to me? So far, I have "Principles of Data Conversion System Design" by Razavi and "CMOS Circuit Design, Layout and Simulation" by Baker, Li and Boyce.