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I want to design an FSM for a fare payment system for public transport:
One that follows the flow I described::
Idle — the system is in standby
Read — the system reads the payment medium
Validate — the system validates the transaction
Grant — access granted
Deny — access denied
Error — connectivity or system failure
And this is the variable
But I would like to know:
One that follows the flow I described::
Idle — the system is in standby
- Waits for the user to present the card (card_present = 1).
- If no card is detected, it remains in Idle.
- If a card is detected, it transitions to Read.
Read — the system reads the payment medium
- Attempts to obtain the card information.
- If a fare request signal (request_fare = 1) is received, it transitions to Validate.
- If no request is received or there is a communication failure, it transitions to Error.
Validate — the system validates the transaction
- Checks two conditions:
- The trip quota (greater than 0) is available.
- If both conditions are met, it transitions to Grant.
- If either condition fails, it transitions to Deny.
Grant — access granted
- Activates the output access = 1.
- Deducts the trip_quota and decreases balance by 1.
- After granting access, it returns to Idle.
Deny — access denied
- Keeps the output access = 0.
- Displays an error for insufficient trip_quota or no remaining trips.
- After denying access, it returns to Idle.
Error — connectivity or system failure
- Stops the validation process.
- Sets access = 0.
- Remains in this state until reset or connectivity is restored.
- Then returns to Idle.
And this is the variable
fsm:
// Entradas
input wire clk;
input wire reset;
input wire card_present;
input wire request_fare;
input wire [7:0] balance;
input wire [7:0] trip_quota;
// Salida
output reg access;
// Variables de registro
reg [2:0] current_state;
reg [2:0] next_state;
// Definición de estados
localparam IDLE = 3'b000;
localparam READ = 3'b001;
localparam VALIDATE = 3'b010;
localparam GRANT = 3'b011;
localparam DENY = 3'b100;
localparam ERROR = 3'b101;But I would like to know:
- Is it possible to simulate this in Verilog, especially the operations of balance verification or fare deduction?
- How can I detect undeclared states?
- And is it important to implement and test it on an Altera/Cyclone FPGA board, or is it enough to verify the design through waveforms in simulation?
- With this execution flow and design logic, is it enough to achieve proper functionality as expected in real life? Is the implementation realistic?
