Yes,I am giving regular 50% duty cycle input at the top gate side ,And this is the result.and the bottom side is been supplied with a constant high signal.

Yes,I am giving regular 50% duty cycle input at the top gate side ,And this is the result.and the bottom side is been supplied with a constant high signal.

Hi;
I want to design this circuit. There's something I'm curious about.
I want one answer. Please help me.
When creating the pwm signal, do we add the dead time in the software.
Or does it create LT1160 integrated?
Thank you in advance for your answers.

MOD: Link to original Thread
https://forum.allaboutcircuits.com/threads/help-with-lt116.165408/post-1456902

 

According to the LT1160 datasheet "The internal logic prevents the inputs from turning on the power MOSFETs in a half-bridge at the same time. Its unique adaptive protection against shoot-through currents eliminates all matching requirements for the two
MOSFETs."
On that basis you should not need to add dead-time in software (but it wouldn't hurt to do so).
When designing things you should always check the datasheets of components you plan to use.