If you upload my collection, there are models and symbols in it. At the same time, the symbols contain links to the necessary libraries (as opposed to symbols from the Yahoo group). To simulate enough to put a symbol on the scheme and do not refer to the library.
link:
http://bordodynov.ltwiki.org

Hey @Bordodynov I also looked at the link you provided. i was wondering if you had 74HCT365/74HC365 Model. As well. Regards

 

Hi i am a newbie in LTspice. I tried importing 74HC365 Hex Bus Driver with 3-STATE Outputs, to my schematic. But i am having a challenge with the pin count mismatch. the error reads that "the instance has fewer connection terminals than the definition."
i dont know how to solve this problem as i have matched the pins correctly according to the LIb file. One more thing, the lib file.SUBCircuit section has 14 pins yet the datasheet has 16 pins. I have tried to create both 14 and 16 pins IC but still getting the mismatch error. Does anyone know how to solve this. Here is the datasheet and .asy and sub files to the part. And can the alternative circuit i have designed be used in place of the IC? Thanks

 

the lib file.SUBCircuit section has 14 pins yet the datasheet has 16 pins.

Many Spice models don't explicitly include the power supply pins (Vdd, Vss or Vcc,Vee).

 

Many Spice models don't explicitly include the power supply pins (Vdd, Vss or Vcc,Vee).

Thank you Alec_t for the feedback, what could you suggest that i rectify in the library file with regards to PWR and GND?
regards

 

You can't use this file. Its syntax is not compatible with LTspice.

 

Thanks

You can't use this file. Its syntax is not compatible with LTspice.

for the reply, could you advise me the closest component inLTspice that can be used in place of the device. Thanks

 

Here's the hierarchical model of the chip you need. I warn you that delays are not modeled accurately!

 

I corrected the model. Now the signal delay is more real. I reloaded the file.

 

I corrected the model. Now the signal delay is more real. I reloaded the file.

thanks so much for the timely assistance. I will try it

 

I corrected the model. Now the signal delay is more real. I reloaded the file.

Thanks for the help, i appreciate, i will definitely give it a try