I've been struggling to upload so I'll post info on the next post...

 

(two screenshots attached)

Hi everyone, Im trying to make a digital circuit that receives a signal for a certain button, and then outputs in Binary coded decimal. I've tried simulating the circuit on ISP lever and got the following error messages:

Instantiating primitives...
Linking 'C:\ispLEVER_Classic1_6\ispcpld\lib5\g_2or.bl1'
Linking 'C:\ispLEVER_Classic1_6\ispcpld\lib5\g_input.bl1'
Linking 'C:\ispLEVER_Classic1_6\ispcpld\lib5\g_inv.bl1'
Linking 'C:\ispLEVER_Classic1_6\ispcpld\lib5\g_output.bl1'
Logical Error 3509: Output 'd' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'a' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'b' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'c' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'd' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'a' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'b' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'c' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'd' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'a' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'b' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'c' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'd' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'a' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'b' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'c' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'd' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'a' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'b' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'
Logical Error 3509: Output 'c' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_output'

BLIFLINK complete. Error: 20. Warning: 0. Time: 1 second

Done: failed with exit code: 0001.


Im trying to attach images of the circuit and attempted simulation but the forum is preventing me from doing so. Ill see if I can upload it online and post the link here...

 

I think we will need more information. Circuit, uController, code, compiler, ...

 

I don't have any code, I made it with a schematic. I'm using ISPLever Classic.

I don't know what uController is and the circuit was provided as an attachment in my last post.

I think the schematic should show whether or not there is a problem with my circuit. It must be a problem in logic

 

Oh if by uController you mean microcontroller, this isnt going to be implemented on a microcontroller, it will be implemented on a 22V10 GAL digital integrated circuit.

However I think its implementation or purpose shouldn't matter as the problem arising from this circuit is logical in nature and so shoudn't matter which hardware it will eventually be implemented onto. correct me if I'm wrong

 

Is no one able to help???

 

I don't think it's a logic problem. I think you do not know how to use the software. (Nor do I.)

 

I know how to use the software, I have designed and tested a number of designs that worked smoothly on there. In fact, the project I am working on has 6 components, all of which work except for this one.

But are you saying the logic schematic displayed on the attachment is logically fine?

 

If there is anything you don't understand from the screen shots let me know and I'll clarify but I presume this is fairly similar to other packages for designing digital schematics and simulating them?

On the simulation schematic the waveforms for I next to them are the inputs I made and the O is for outputs which are obviously blank as the simulation is supposed to provide me with the resulting outputs

 

You appear to have 6 outputs named 'a', six named 'b', etc. Are the error messages saying that those are shorted together because of the common names?

What is " functional_block 'g_output"?

As I said, I am not familiar with the software.

 

Thats correct, if you look at the schematic there are 6 outputs named a, but those are all supposed to be the same output. I just made the same output 6 times because if I only had the one a, b, c, d it would get very messy. It should be ok to do that, Im sure Ive done it successfully on other components of the design although Ill go back through and check to ensure Ive successfully used this method before.

functional_block 'g_output' is the component that represents the output, it has a triangle, square etc on it

 

I just changed it so that there is only 4 outputs and ran the same simluation and got:

Top-level file: 'studentidtobcd.bls'
Instantiating primitives...
Linking 'C:\ispLEVER_Classic1_6\ispcpld\lib5\g_2or.bl1'
Linking 'C:\ispLEVER_Classic1_6\ispcpld\lib5\g_buf.bl1'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_buf'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_buf'
Linking 'C:\ispLEVER_Classic1_6\ispcpld\lib5\g_input.bl1'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_input'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_input'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_input'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_input'
Linking 'C:\ispLEVER_Classic1_6\ispcpld\lib5\g_inv.bl1'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_79' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_79' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_79' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_79' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_80' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Logical Error 3509: Output 'N_79' in upper-level source 'studentidtobcd' can't be redriven to functional_block 'g_inv'
Linking 'C:\ispLEVER_Classic1_6\ispcpld\lib5\g_output.bl1'

BLIFLINK complete. Error: 20. Warning: 0. Time: 1 second

Done: failed with exit code: 0001.

 

The new schematic looks like this (attached).

As can be seen, there are only 4 outputs now and its still not working

 

The schematic looks correct, but something in the setup / definition limitations is causing an error. (I also am not familiar with the software, though it is similar to Xilinx Platform for FPGA in Schematic mode).

Does your device have enough gates and I/O for implementation?

Is there a way you can actually read the Hardware Definition Language file that is generated from your schematic? If so, do you understand how to read the particular HDL?

There aren't many here who have access to every possible software and hardware combination, though HDLs can be similar, each implementation has it's own quirks, similar to C or Basic.

If you can post the generated HDL code generated by the tools schematic editor, if it is simlar to VHDL, somebody may be able to spot where a net is tied to a conflicting net (from running out of logic elements, having more I/O than is available, etc). Just looking at the schematic, it should run in Logisim (Free logic simulator, give it a try!).

If it doesn't behave correctly in Logisim, you can usually spot your error easily due to the way the simulation is displayed. Logisim is ONLY a logic simulator, not an HDL Generation package, however, people have built virtual CPUs in it, so it is very powerful.

 

Ok where can i get a copy of logisim?

This is very frustrating as I have 6 IC's all embedded in 1 hierarchical design IC and all of it functions well except for this one component, if I can get it to work it will be so satisfying watching each component output some bits onto the next component in sequence, starting with a simple clock and outputting my final spec at the end. everything is working literally excepted this one component.

I dont think its an issue with space as the 22V10's can have up to 100 gates and whether I test this component alone or in sequence with the rest of my design the errors all fall on this one component so there is definitely something it doesnt like in there.

I am using ABEL, an old HDL before Verilog and ABEL but its a fairly simple language so hopefully it will make sense if I can figure out how to output an ABEL file. Thanks for responding, much appreciated.

 

Logisim Home Page That link has information about Logisim, extra modules you can download, and the download link for the latest version from sourceforge.net

Have you tried writing your system directly in ABEL? i.e. write the raw HDL code for the simplified version and have it generate a valid output file?

 

I've just downloaded a copy of logisim and am currently inputting the same circuit into it, to see what I can find out.

What particular process should I run in order to give you some useful information?

 

thatoneguy unfortunately I struggle with ABEL. I will give it a go though as it's probabily worth having an attempt. Its for a project that has to be done for Monday so that's why I abandoned ABEL and wrote the whole thing with schematic design but I can at least have a go at making this one component in ABEL

 

I've just downloaded a copy of logisim and am currently inputting the same circuit into it, to see what I can find out.

What particular process should I run in order to give you some useful information?

Just wire up the gates on the grid, and pick "simulate", if you have a clock in the system, the lines will be black (low) or green (high). If the design isn't clocked, it behaves as a state machine, only responding to input changes (such as switches). If it simulates and produces the output you want, then the design is logically sound.

There isn't a way to plot an output waveform of the simulation, AFAIK, you only need to add LEDs and look for the pattern you'd like to have on the output based on the inputs.

 

As I predicted, ABEL didn't work for me (It never does for some reason).

Here is my attempt at some code:



MODULE StudentIDtoBCDinABEL

TITLE 'Student ID to BCD in ABEL'

"Input pins
Two, ZeroA, ZeroB, ThreeA, Four, ThreeB, Seven, Six pin 1,2,3,4,5,6,7,8; "Inputs"

"Output pins
a, b, c, d pin 1,2,3,4; "Outputs" istype 'com'; "Outputs"

In_s = [Two, ZeroA, ZeroB, ThreeA, Four, ThreeB, Seven, Six]; "8-bit number"
Out_s = [d,c,b,a]; "4-bit number"

truth_table ( [In_s] -> Out_s)
[ 1, 0, 0, 0, 0, 0, 0, 0] -> 2;
[ 0, 1, 0, 0, 0, 0, 0, 0] -> 0;
[ 0, 0, 1, 0, 0, 0, 0, 0] -> 0;
[ 0, 0, 0, 1, 0, 0, 0, 0] -> 3;
[ 0, 0, 0, 0, 1, 0, 0, 0] -> 4;
[ 0, 0, 0, 0, 0, 1, 0, 0] -> 3;
[ 0, 0, 0, 0, 0, 0, 1, 0] -> 7;
[ 0, 0, 0, 0, 0, 0, 0, 1] -> 6;

test_vectors ( [In_s, IncDec] -> Out_s)
[ 1, 0, 0, 0, 0, 0, 0, 0] -> 2;
[ 0, 1, 0, 0, 0, 0, 0, 0] -> 0;
[ 0, 0, 1, 0, 0, 0, 0, 0] -> 0;
[ 0, 0, 0, 1, 0, 0, 0, 0] -> 3;
[ 0, 0, 0, 0, 1, 0, 0, 0] -> 4;
[ 0, 0, 0, 0, 0, 1, 0, 0] -> 3;
[ 0, 0, 0, 0, 0, 0, 1, 0] -> 7;
[ 0, 0, 0, 0, 0, 0, 0, 1] -> 6;


END