Justtrying is asking you if your data is flowing from 1) FF/A to FF/D or from 2) FF/D to FF/A.

If the data flow is 1), then the inputs of FF/A is important and it was not shown clearly in your picture

Allen

we was taling about the 1st picture on 1st page...where did u see A thr? For question 1.

 

ronybhai, it is important that you always look at how the data flows trough the circuit. While by convention circuits are usually drawn with data flow from left to right, it may not be always true. Example that you posted (textbook scan) is one such example and is getting you off track right now. Examine each individual FF in the circuit, where its input is coming from and where its output is connecting to. Once you do that, you will be able to write out states for j/k and get the outputs.

 

I am sorry, but I am very confuse on how to start.
Can I fnd any examples like these on youtube?

 

can you please write what you understand about the example that you posted? Do you know how that table was generated?

 

can you please write what you understand about the example that you posted? Do you know how that table was generated?

This is Synchronous counters?
Not sure how the table is generated

 

Is it possible to provide with any related examples? thanks

 

has this been covered at all? initially it sounded like this was an example covered in class. But now I am doubtful.

try doing questions 14 and 16 here. These will check your basic understanding of JK FFs. Please do not cheat by looking at the answer first. If you understand the basics, then proceed further.

 

I know how to do this...we covered it already and had exam on it also...just have to follow the truth table for JK flip flop to draw the output based on the clock given

 

wel....I will try to see what can i figure it out by reading the book... or ask my frnd if they knw...thanks for ur help....and ur time

 

All you do here is apply that principle. Output of one FF acts as input for the other - that is why I was asking you about direction of data flow. On which FF does the data appear first?

maybe this will help you.

 

K has inverter on it..so it will be opposite of Data in right?

 

Yes, inverter outputs the opposite state of the input. For questions like these please refer to data sheets and write out a small truth table for yourself and those who are trying to help.

 

ok...i think i did the truth table...let me post it here..can u see if it is correct?..thanks

 

this is the table for the 1st question
Not sure tho..thanks

 

K has inverter on it..so it will be opposite of Data in right?

Correct.

It's not much in the way of make some effort, but it is something. So lot's go with it.

Make a table like the one to the right of the circuit, but add two columns right before each x column and use these to write down the J and K values for that FF. So the first two columns after "Data In" will be J3 and K3.

Can you fill in that column? If so, post it here. Don't take the time to scan it, just put it into a table in the post, like this:

Clk|Data||J3|K3|x3||J2|K2|x2||J1|K1|x1||J0|K0|x0|
1|0||||0||||0||||0||||0|
2|1|||||||||||||||||
3|1|||||||||||||||||
4|0|||||||||||||||||
5|0|||||||||||||||||
6|1|||||||||||||||||
7|0|||||||||||||||||
8|1|||||||||||||||||
9|0|||||||||||||||||
10|1|||||||||||||||||

Remember that the FF outputs change after the clock's rising edge in response to what was on the inputs before that edge. This means that you need to put the new x values on the row after the one containing the inputs that cause it.

For now, just fill in the J3 and K3 columns and, if possible, take a shot at the x3 column. If things start making sense, then by all means try more.

 

Okay, you posted your table before I got my last post finished.

You have the right idea, but you aren't taking into account the delay in the signal chain as it walks from FF to FF.

But you've made good progress. Read what I have under my table and take another shot at it.

 

oo..I made error on my table...wrote down the data in incorrectly...here is correct one...not sure if it right...

 

Correct.

Clk|Data||J3|K3|x3||J2|K2|x2||J1|K1|x1||J0|K0|x0|
1|0||||0||||0||||0||||0|
2|1||||1||||1||||1||||1|
3|1||||1||||1||||1||||1|
4|0|||||0||||0||||0|||0|
5|0|||||0||||0||||0||0||
6|1|||||1||||1||||1||1|
7|0|||||0|||||0|||0||0||
8|1|||||1|||||1||||1||1|
9|0|||||0|||||0||||0||0|
10|1||||1|||||1||||1|||1|

It doesnt look right....the clokc is going down....so how does it change the output?

 

LOL professor goykadosh will explain it tomorrow. (I'm in your class) Yeah this homework was ridiculous the text does a horrible job in explaining this chapter bro. See you in about 10 hours hahahaha this was a funny post. Good progress.

 

It doesnt look right....the clokc is going down....so how does it change the output?

What do you mean the clokc is going down?

Let's look at this one clock cycle at a time. Before the first clock, what are the inputs at all the FFs across the circuit? They are

Clk|Data||J3|K3|x3||J2|K2|x2||J1|K1|x1||J0|K0|x0|
1|0||0|1|0||0|1|0||0|1|0||0|1|0|
2|1|||||||||||||||||
3|1|||||||||||||||||

Knowing what the J and K inputs are to each FF before the clock lets you determine what the outputs are after the clock.

Clk|Data||J3|K3|x3||J2|K2|x2||J1|K1|x1||J0|K0|x0|
1|0||0|1|0||0|1|0||0|1|0||0|1|0|
2|1||||0||||0||||0||||0|
3|1|||||||||||||||||

Now complete the second row for the rest of the signals.

Clk|Data||J3|K3|x3||J2|K2|x2||J1|K1|x1||J0|K0|x0|
1|0||0|1|0||0|1|0||0|1|0||0|1|0|
2|1||1|0|0||0|1|0||0|1|0||0|1|0|
3|1|||||||||||||||||

Now let the clock happen and update the outputs of the FFs.

Clk|Data||J3|K3|x3||J2|K2|x2||J1|K1|x1||J0|K0|x0|
1|0||0|1|0||0|1|0||0|1|0||0|1|0|
2|1||1|0|0||0|1|0||0|1|0||0|1|0|
3|1||||1||||0||||0||||0|

And so on.

At some point, what you should notice is that the JK inputs to each stage are always opposite each other. This means we can completely ignore the JK=00 and JK=11 behavior of the JKFF. So, if J always equals the output from the prior stage and K is always opposite that value, what IS the behavior of a JKFF?