Hey guys,
I have a hard time to find the solution of the attached problem. Its about gates have delay....

 

Have you drawn up a timing chart as yet? That will clarify things.

 

you are right but I am having hard time with timing chart...
can you please explain more about it?

Thank you

 

Make a column with all the nodes of the circuit. Each will correspond to a row with a timeline. Draw the signals as they appear. This will let you understand intuitively the delay propagation.

Your chart should look like this:


Your vertical increment should be 1ns.

 

Set the logic up with the initial state levels. Identify the static output levels, and make the change in C. See when the changes go though the gates.