i try to design a fsm to detect the sequence "1101" , inputs: a 1bit,rest,clk output:y
when the sequence is detected y=1 , i have code it by vhdl but in simulation it dont work
please help me
library ieee;
use ieee.std_logic_1164.all;
entity machine is
port(
rst,clk,a : in std_logic;
y : out std_logic);
end machine;

architecture arc of machine is
type m_state is (s1,s2,s3,s4,s5,s6,s7,s8);
signal state : m_state :=s1;
begin
process(clk,rst) is
begin
if (rst='0') then
state <=s1;
elsif(rising_edge(clk)) then
case state is
when s1 =>
if a = '1'then
state <=s2;
else
state <=s1;
end if;
when s2 =>
if a = '0'then
state <=s1;
else
state <=s3;
end if;
when s3 =>
if a = '0'then
state <=s4;
else
state <=s1;
end if;
when s4 =>
if a = '0'then
state <=s1;
else
state <=s5;
end if;
when s5 =>
state <=s1;
when s6 =>
state <=s1;
when s7 =>
state <=s1;
when s8 =>
state <=s1;
end case;
end if;
end process;

process(state)
begin
case state is
when s1 | s2 | s3 | s4 | s6 | s7 | s8 => y<='0';
when s5 => y<='0';
end case;
end process;
end arc;

 

Perhaps if you were to properly format your code, people would be more interested in looking at it. Consider using CODE tags.

It sounds like you made the all-too-common mistake of throwing all the code together and THEN seeing if, by some miracle, you happened to get it exactly right. This is a VERY poor way to develop code (or solve most engineering problems).

Start off simple. Make a machine that can recognize just the sequence "1011", meaning that it will accept it only if that exact, four-bit sequence is entered. Test it to make sure it behaves like this. Then pick one or two enhancements that should make it recognize additional allowed sequences and expand the code to handle those cases. And then TEST it to make sure that it does recognize the new sequences but still doesn't recognize sequences it shouldn't.

It would also help you (and anyone trying to read your code) to document what knowledge about the history of the machine each state represents.

 

As said above,

Without the formatting, its very hard to read,

Do you need to use a state machine ?

are you allowed to use a shift register and a gate,
clock in the data,
4 bit shift register, and the parallel output of the shift register,
have a gate that is '1' when input is the required pattern,
just a thought

 

thank you , i have made the correction , but when i try it in rral simulation using inputs switchs in tina software it dont work