So…. It was distorted due to a high input level?

 

So…. It was distorted due to a high input level?

Yes. 10db is a little too much so I'll test with with some 3 and 6db inline components to see where the nonlinearity begins. The distro amp is only $20 so I'm not expecting hi-fidelity, just sufficient locking signal for devices with external frequency standards.

Magenta is the GPS signal input before the attenuator, Blue is the video distro amp output. You can see the amplifier phase shift (cables are also not exactly the same length) and the reduction in signal voltage level.

I still need to make the 3.3 TTL digital output board.

 

Working on the sine to digital converter circuit on a vectorboard with some copper shielding film to keep it 'stable'.

Using a 2K pot to bias the CD74HC132E with a 1V PP signal from the generator and a 500 ohm load on the digital output pin to keep the thing from oscillating too badly.


Digital output frequency read-back on the counter.

Adjust the 2K pot for ~50% duty cycle within the IC gate trigger ON/OFF voltage zone. With some spurious signal generation at the digital toggles.


At the bias trigger point we get a spurious signal during the output toggle.


Almost 60MHz for ~10 us while in linear no-mans land. The damping resistors will be a critical component for stability here.

 

Added triple bypass caps on the vectorboard and a bias filter on the PCB design.



The spurious signal looks like a normal ring now.

 

JLC prototype boards with just the square wave circuit running.


Have a series 100 ohm resistor for the voltage divider for adjusting the duty cycle. 100 ohms.

133 ohms.

3.3V logic rise time looks OK.

 

Decent 3.3 clock shape (unterminated input and outputs, so lots of reflections) to 20Mhz from a 1v PP sinewave.

 

I like the 74HC132/ signal conditioning schematic at work, good point also weak signal RF sometimes can use more preamp.
A quality scope probe on a warm counter, the use of scope, sufficient amplitude and outputting clean NAND gate edges.
If a good counter front end is having trouble then the circuit probably can benefit from conditioning if accurate frequency is needed.
Thanks for taking time to show the signal integrity is more than just accurate reference, the schematic might improve what I have.

 

Finally got around to connecting the GPS time reference into the server NTP (network time protocol) system using the serial output from the receiver.

The serial data is connected to the server with a USB-RS232 adapter, the Linux gpsd daemon formats the 9600bps serial data into standard shared memory segments for the ntpsec time daemon to use as a local high precision master clock with other clock sources. https://gpsd.gitlab.io/gpsd/gpsd-time-service-howto.html
That data can also be used my several types of clients for viewing and logging.

xgps is the one I'm using here.

https://gpsd.gitlab.io/gpsd/xgps-sample.html

As you can see, the house is not moving too fast and is not too high.
Height Above Ellipsoid (HAE)
MSL stands for “mean sea level“

Both bounce around +-30 ft at this location.

 

Final version of the PCB, no buffer amp.






Logic level outputs.
Top 1: 3.3v pins on the pin header
Bottom 2: BNC output with series damping resistor before the board output connector
https://github.com/nsaspook/gpsbuf/tree/no_buffer

 

Up to 40 MHz (limit of the cheap signal generator) with the sine to digital level CD74HC132 converter board.


Center analog trace on the BNC input pin.

The input NAND gate bias shift needs correction (using R7) for close to 50% duty cycle output.

https://www.ti.com/lit/ds/symlink/c...ttps%3A%2F%2Fwww.ti.com%2Fproduct%2FCD74HC132

 

Thanks for sharing all your efforts.