I am currently working on frequency multipliers now. Is there a frequency multiplier topology where the input and output can be on the same duty cycle? For example, if input frequency have 20% of duty cycle then the output frequency signal should be 20% of duty cycle. Generally using PLL method, if frequency is multiplied with even numbers then you will give 50% of duty cycle. But ı want to get same duty cycle with input. Thank you for your help in advance.