finding Vbe in NPN Biasing

WBahn

Joined Mar 31, 2012
32,871
Hello Mr. Chips i have recreated the plot you showed.
In mosfets the platue line is called saturation region and the ramp line is the linear region.
So in bjt its the opposite?
Thanks.

View attachment 289196
This is a common point of confusion for people at your level -- I had the same question and the same confusion. We usually learn about BJTs and that "saturation" means that Vce has gotten so low that, even with more base current, we can't increase the collector current any more. But then we see the same term used in relation to FETs, but now it seems to mean the opposite. The key is that the term "saturated" is being applied to one phenomenon in BJTs and to a different phenomenon in FETs -- this is almost unavoidable since the underlying physics behind how each type of device operates is different. In both cases it is meaning that something has gotten to point where it basically can't increase any further.

In a FET, if you put just a little voltage between gate and source, the ability to conduct current "saturates" as a certain level regardless of what the drain-source voltage is (above some level). But if you increase the gate-source voltage, you can get more drain current.
 
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