Below there's a picture of the circuit I'm simulating. I've also attached the asc file. The op amp used is MC33172D. I tried to find a model online but I didn't have success importing it to LTspice. So I'm using the LT1112. I have the following questions regarding the circuit operation and the simulation:

1- What are the purposes of C3 and C4? Coupling capacitors?
2- Why is the output signal a little bit shifted right?
3- Why is the output signal a little bit less? diode drop?
4- At last, why the output peak voltage is less in the negative cycle?

 

1- What are the purposes of C3 and C4? Coupling capacitors?

C3 is a power filtering capacitor; C4 is a coupling cap.

2- Why is the output signal a little bit shifted right?

There are two sources of the shift. Capacitor C2 adds a little. But capacitor C4 is the main source. Since C4 is the input to the op-amp, it introduces lag represented by 3 x the RC time constant. I’m not sure where you got your values from, but IMHO C4 is too large. It may be needed, but I’d use 0.1μF. I can’t read the resistor value, so I recommend you do the calculations for the expected shift and see if they are congruent to your results.

3- Why is the output signal a little bit less? diode drop?

No. Likely because op-amps aren’t truly rail-to-rail. If you input 5V, you’ll always get less than 5V out. The LT1023 only goes to 4.3V max. I didn’t look up the LT1112. The min/max rail outputs can be found on the datasheets. There are rail-to-rail op-amps that get closer to Vcc but you never get 100%.

4- At last, why the output peak voltage is less in the negative cycle?

During the negative cycle. The caps are discharging. So the envelope will dip.

 

hi,
I would say C3 purpose is to act as a filter to remove any high frequency noise.

Remove C4 , it unbalances the Vout at 'ct', with the C4 in the signal is offset from zero.

Also R1/D1 are not the same loading on the negative half cycle as the positive half cycle, as are D2 and R2.
Reduce R1 to 460K

The delay at the output Vout is due to the charge/discharge cycle of C2

Who designed the circuit.?

E

 

Something like above.


Regards, Dana.

 

What is the exact purpose of this circuit?

 

What is the exact purpose of this circuit?

The input is a CT, that's why I put a current source to simulate it. The final output is used to feed a comparator.

 

Why so much gain?
What is the minimum signal you want to detect (comparator trip point)?

 

Of course this can be done with a UP pretty easily.....in case
you also need intelligence and other control in system.


Regards, Dana.

 

hi Blue,
Did you try making those changes to your LTSpice circuit as my post #3.?

E

 

Eric, I haven't tried it. I'll do it in a while. I have attached below the circuit which is connected to the output of the circuit in post #1.

 

Another source of phase shift (delay) is D2-C3. The equivalent resistance of D2 forms an R-C circuit with C3. This circuit has attenuation and phase shift, both of which change as a function of the frequency of the signal.

ak

 

1- What are the purposes of C3 and C4? Coupling capacitors?

C3 is a power filtering capacitor; C4 is a coupling cap.

2- Why is the output signal a little bit shifted right?

There are two sources of the shift. Capacitor C2 adds a little. But capacitor C4 is the main source. Since C4 is the input to the op-amp, it introduces lag represented by 3 x the RC time constant. I’m not sure where you got your values from, but IMHO C4 is too large. It may be needed, but I’d use 0.1μF. I can’t read the resistor value, so I recommend you do the calculations for the expected shift and see if they are congruent to your results.

3- Why is the output signal a little bit less? diode drop?

No. Likely because op-amps aren’t truly rail-to-rail. If you input 5V, you’ll always get less than 5V out. The LT1023 only goes to 4.3V max. I didn’t look up the LT1112. The min/max rail outputs can be found on the datasheets. There are rail-to-rail op-amps that get closer to Vcc but you never get 100%.

4- At last, why the output peak voltage is less in the negative cycle?

During the negative cycle. The caps are discharging. So the envelope will dip.

C4 shouldn't be too critical, it only has to be adequate to pass the lowest audio frequencies of interest. However C3 IS critical. There is a maximum value that this can be before you start seeing "diagonal clipping" or "failure to follow distortion." There is a formula for the optimum value for C3, but it's lost in the recesses of my cranium right now. I'll try to dredge it up. It is dependent on both the bandwidth AND modulation depth.