Emulating a Tri-state Buffer

Thread Starter

jpanhalt

Joined Jan 18, 2008
11,087
I am having difficulty getting an NXP LPC2134 into bootload mode for ISP using simple mechanical switching. An alternative is to let the RS232 programmer control DTS/RTS to get into that state. NXP gives an interface for that which uses an xx125 (tri-state, non-inverting buffer):

1586811694138.png

My favorite surplus store in Cleveland (ESI) is effectively closed for the time being. In the NXP design, A1 is grounded. I wonder whether the "high impedance" state of a PIC is sufficiently high to emulate the "open" state for that chip. For example, when OE1 is low, YI would be an output set to low. When OE1 is high, TRIS for the Y1 pin would be set (i.e., input). There would be no WPU. Maximum "open" leakage current for the 125 is 10 uA.
 

Thread Starter

jpanhalt

Joined Jan 18, 2008
11,087
Thanks.

I am considering the 12F1840/12F683, as I have plenty and only need two such buffers. Here is what I thought was relevant from the datasheet, but I wasn't sure my interpretation was correct:

1586813938984.png

John
 

crutschow

Joined Mar 14, 2008
34,285
In all cases the leakage current is low enough that it wouldn't affect the output logic levels from whatever is driving the bus.
 

Thread Starter

jpanhalt

Joined Jan 18, 2008
11,087
My design is currently on paper. The code will be incredibly simple. A project for a cold and rainy tomorrow.

I am far less optimistic it will work. I have spent 28 hours (not exaggerated) over the past 3 days trying to get the $@%& thing to be recognized by my FTDI TTL RS232-3V3 adapter. I even fired up X-CTU as a terminal emulator and an oscilloscope to see the signal and a dead response.

John
 
Last edited:

OBW0549

Joined Mar 2, 2015
3,566
I wonder whether the "high impedance" state of a PIC is sufficiently high to emulate the "open" state for that chip. For example, when OE1 is low, YI would be an output set to low. When OE1 is high, TRIS for the Y1 pin would be set (i.e., input). There would be no WPU. Maximum "open" leakage current for the 125 is 10 uA.
I recall doing that once or twice, years ago: write a "0" to the appropriate bit in the LATx register, then write the data stream to the corresponding bit in the TRISx register.

I can't imagine that there would be much difference in the behavior of the PIC output vs. the 74HC125 when in the OFF state; both would show a very high impedance with perhaps a few microamps of leakage.

But what about the ON state? How do their drive capabilities compare? Maybe the 125 satisfies some output drive requirement that the PIC cannot?

Dunno...
 

Thread Starter

jpanhalt

Joined Jan 18, 2008
11,087
For the MC74HC125A, inputs and outputs are about the same as PIC's:

1586826963655.png

Of course,PIC's are generally limited to ±25 mA per pin output. That should not be a problem as the NXP LPC2134 has similar limits.
 
Top