I am confused I want to know what is difference between always and assign and where they use

program 1st
module and2gate (A,B,Y);
input A,B;
output Y;
assign Y=A&B;
endmodule

program 2st
module and2gate (A,B,Y);
input A,B;
output Y
reg y
always@(AorB);
begin
Y<=A&B;
end
endmodule

which program is right please someone explain where we use always and assign syntax

 

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