Hello, guys i read about d flip flops in cmos and asynchronous reset from Neil H. E. Weste 'CMOS VLSI Design' book and i dont unsterstand in the figure below why the nand gate has a clock signal and how we can implement a nand gate like this. I know how i can implement a simple nand gate in cmos but this nand gate has clock signals attached.
edit: i just found what is a tri-state register:
Is the above nand gate the same as the tri-state register. The equivalent circuit of a clocked nand gate is a nand gate and a transmision gate?
I would appreciated if anyone could help me.
Thanks
edit: i just found what is a tri-state register:
Is the above nand gate the same as the tri-state register. The equivalent circuit of a clocked nand gate is a nand gate and a transmision gate?
I would appreciated if anyone could help me.
Thanks
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