Develop state diagram for the Finite state machine?

Thread Starter

Gonzalo Armbrust

Joined Jun 28, 2015
"The decimal digits 0 through 5 are encoded as 3-bit binary numbers. They are transmitted in disjoint windows of length 3 least significant bit first and are input to a Mealy circuit model. The circuit generates an output of 1 (0) when the third bit is received if the 3 bits have been even (odd) parity; the circuit output is a don’t-care for the first 2 bits. Construct an incompletely specified table for the circuit"

I'm not sure where to start on this one, could anyone give me a hint to get me started?


Joined Mar 31, 2012
I would say the first thing would be to draw a diagram of the input stream to the machine and what the outputs should be at each step along the way.