I'm trying to design the following digital system:
8 inputs (in each clock rise, 8 bits are received).
8 outputs
CLK: input -----> Output
1:::: 00101010 -> 00100000 (index 3 = 1)
2:::: 01001001 -> 00001000 (index 5 = 1)
3:::: 01010101 -> 00000100 (index 6 = 1)
4:::: 01001000 -> 01000000 (there is no '1' at indexes 7,8 of input, so we start from the beginning, and therefore index '2' = 1).
How would you design such system using digital logic? (FFs, logic gates, counters, etc).
Thank you.
8 inputs (in each clock rise, 8 bits are received).
8 outputs
CLK: input -----> Output
1:::: 00101010 -> 00100000 (index 3 = 1)
2:::: 01001001 -> 00001000 (index 5 = 1)
3:::: 01010101 -> 00000100 (index 6 = 1)
4:::: 01001000 -> 01000000 (there is no '1' at indexes 7,8 of input, so we start from the beginning, and therefore index '2' = 1).
How would you design such system using digital logic? (FFs, logic gates, counters, etc).
Thank you.
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