at first picture i switch 0 and 1 (actually 0 is count down and 1 is count up) but in k map i already write is right.
and why isn't work

 

Thanks for showing some work. It's appreciated.

But it would sure be helpful to get a better description of what it is doing wrong beyond "isn't work".

What, specifically, IS it doing that it isn't supposed to be doing?

What steps have you taken to debug the design?

Have you checked to see if the behavior is or is not consistent with the schematic?

Have you measured the values on the various nodes when it is misbehaving and determined which, if any, aren't at the values they should be?

 

Thanks for showing some work. It's appreciated.

But it would sure be helpful to get a better description of what it is doing wrong beyond "isn't work".

What, specifically, IS it doing that it isn't supposed to be doing?

What steps have you taken to debug the design?

Have you checked to see if the behavior is or is not consistent with the schematic?

Have you measured the values on the various nodes when it is misbehaving and determined which, if any, aren't at the values they should be?

oh sorry, i forget to tell what is ploblem. when i start the simulation 7segment just have 0-3-0-3-0-3 it should be 0-3-1-4-2-5 i don't know why

 

Welcome to AAC!

why isn't work

What isn't working?

Is this homework?

 

Welcome to AAC!

What isn't working?

Is this homework?

it is not home work, it is my project.

 

it is not home work, it is my project.

What project? Is it related to course work of any kind?

 

oh sorry, i forget to tell what is ploblem. when i start the simulation 7segment just have 0-3-0-3-0-3 it should be 0-3-1-4-2-5 i don't know why

So, it goes from 0 to 3 just fine. But it is going from 3 to 0 instead of 3 to 1.

That means that the next state that it SHOULD be going to is 0001 and the state that it IS going to is 0000.

Does that not suggest some place that you might start your investigation?

 

What project? Is it related to course work of any kind?

Up-down counter project in Digital course.

 

Up-down counter project in Digital course.

Thanks. That makes it "homework", which is a catch all for any assigned work whose primary purpose is for you to learn something or to demonstrate that you have learned something.

The rules are different for such work. The goal is not to figure out how to solve the problem, but to help YOU figure out how to solve the problem. The interaction is quite different.

 

MOD NOTE: Moved to Homework Help.

 

So, it goes from 0 to 3 just fine. But it is going from 3 to 0 instead of 3 to 1.

That means that the next state that it SHOULD be going to is 0001 and the state that it IS going to is 0000.

Does that not suggest some place that you might start your investigation?

i have rework in the simulation but it is working the same before.

 

i have rework in the simulation but it is working the same before.

Is it working properly in simulation but not in hardware, the other way around, or not working properly in either?

 

Take your schematic and, in some kind of editing program such as Paint (unless you can do it in your schematic capture program more easily) annotate the voltage or logic level on each signal that affects the lsb when the system is in state 0.

Also, you have floating inputs on your flip flops. That's bad. You can get away with it on many simulators (which is a shame), but not in real life (particularly with CMOS). If your circuit in hardware has those pins floating, that might be your problem.

You might also clean up the routing on your schematic. I've seen a lot worse, but you can do a lot better pretty easily.

 

My professor said my project has one mistake on switch SPDT.
is it?

You might also clean up the routing on your schematic. I've seen a lot worse, but you can do a lot better pretty easily.

i just follow my solution, is it wrong?

 

My professor said my project has one mistake on switch SPDT.
is it?

Does it? Seems like they have also give you a strong hint on where to look. What have YOU done to try to determine if that is where the problem is? We've already identified an operating state where it misbehaves. YOU need to examine the value of all the logic in that state that could be causing the observed wrong behavior. So do that and show us what you find.

i just follow my solution, is it wrong?

I have no idea what you mean by this. The correctness of your solution has nothing to do with drawing your schematic so that it is clean and presentable.

 

Nop, there's nothing wrong with the switch. I think you have to check your wiring again. Some of the inputs of U1 and 7476 are floating and I think that's bad. I redrew your schematics and it looks better now.



Now you can start debugging your circuit.

Allen

 

I am still getting 5-2-5-2-5-2 when counting down.

See if you can find the problems.

Allen

 

Your switch (plus inverter) produces logic HI and LO or LO and HI, depending on its position. So the switch itself is not the problem.

It is possible that you have a logic signal coming from the inverted side of the switch that should come from the non-inverted side or vice-versa. That is likely what your professor was indicating. I don't know if that is correct or not.

But if you take your schematic, as if someone else had drawn it and given it to you and asked you to analyze it to determine the count sequence when SW1 is HI, you would find that it should do exactly what the simulator is showing.

So DO the analysis. Make a state diagram of all eight possible states and determine which state each one goes to. Compare that to your intended sequence. Then pick a state that produces the wrong next state and explore the details of your logic implementation to your K-maps. If they agree, then you know the K-maps have an error so work yet further back. If they don't agree, then you have a logic implementation error that should be easy to spot at this point because you know exactly where the two disagree.

 

Nop, there's nothing wrong with the switch. I think you have to check your wiring again. Some of the inputs of U1 and 7476 are floating and I think that's bad. I redrew your schematics and it looks better now.

View attachment 143533

Now you can start debugging your circuit.

Allen

thank you for simulation. but i redrew follow you is just 0 3 0 3 Hmmmm.

 

Something is not right on the outputs of your exclusive OR gates 7486. You shouldn't get grey squares on them. Try using 74LS86 and see if it work.

May be you chose the open collector XOR gates.

Look at my sim at post#16. It should be either red or blue.