I have a 75 MHz clock, and there are input signals for SDA1 and SDA0. Could someone help me understand how much length mismatch between these signals is acceptable?


Let me know if you'd like further clarification or help with the calculations!

 

I have a 75 MHz clock, and there are input signals for SDA1 and SDA0. Could someone help me understand how much length mismatch between these signals is acceptable?


Let me know if you'd like further clarification or help with the calculations!

I'm not sure I understand what a length mismatch is. Are the rising and falling edges supposed to be aligned with each other or do they have some other relationship? What is the setup and hold time for the register the signals are being clocked into? Your clock period is 13.33 nanoseconds so my first guess about what I think you are asking would be one quarter cycle or 3.33 nanoseconds

Setup time for a 74AC74 is about 4.5 nanoseconds with a hold time of 0.5 nanoseconds. You can see where a half cycle delay between the two signals might be problematical.