Hi, can anyone help me explain the meaning of dead-time? Thanks.

Ken-ji

 

I generally associate the term "dead-time" with the applications involving an H-bridge driver. This term is used to describe the brief moment between the h-bridge reversal when at least the two upper legs of the h-bridge are shut-off in order to avoid the potential of turning on the upper and lower legs on one side of the h-bridge at the same time.

If the two legs of the h-bridge on one side are both turned on at the same time, the result can be castastrophic to one or both of the devices involved.

Did you have a particular context in mind for your question?

hgmjr

 

Yeah I think that explains it quite well, I wasn't really sure about what dead-time meant. I had to design this delay circuit which creates the dead-time for a pulse width modulated supply that goes into an inverter. I have the circuit design but I'm not sure how to calculate the value of the variable resistor in order to set a reasonable dead-time. Would you happen to know how to do so? Thanks!

Ken-ji

 

There is no resistance value on your schematic for VR1 and VR2 but You should be able to estimate the dead-time at somewhere between R*C and 2*R*C. Where R is the value set by VR1 or VR2 and C is the 1nanoFarad in the circuit.

As you can see the diode is installed to make the rising edge from the first NAND gate act almost instantly while the transition from high to low from the first NAND gate is delayed by the time constant set by VR1 and C1 or VR2 and C2.

That would work out to somewhere between 1 and 2 microseconds per 1000 ohms of the VR control. For example, if VR1 is a 10K potentiometer and it is set to the midpoint in its travel then you would have between 5 and 10 microseconds of dead-time.

The two signal paths take care of deadtime for each of the two directions.

hgmjr

 

Oh ok, that makes sense. I totally forgot about calculating the time constant from VR and C. Thanks very much!

Ken-ji

 

As you can see the diode is installed to make the rising edge from the first NAND gate act almost instantly while the transition from high to low from the first NAND gate is delayed by the time constant set by VR1 and C1 or VR2 and C2.

I'm a bit confused by this line, could you explain it to me as well as the purpose of the NAND gate? Thank you!

Ken-ji

 

I'm a bit confused by this line, could you explain it to me as well as the purpose of the NAND gate? Thank you!

Ken-ji

Here is my attempt at sketching a Deadtime Diagram in order to clarify the concept.

hgmjr

 

I get it now, the diagrams made it clear for me. Thanks very much again!

 

Hi, I got asked by my tutor how to exactly calculate the dead-time. I know it's delayed by the time constant but to calculate the exact duration of the dead-time, it's not equal to the time constant. I'm not really sure how to calculate it, but I was thinking of the decay of an RC circuit where V(t) = V.e^(-t/tau). Could someone point me in the right direction? Thanks!