Dead time: Why is it implemented on gate side, rather than logic side?

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joe6486

Joined Apr 17, 2019
1
(Context: Class D amplifier)

In most example circuits, I see dead time implemented by adding a resistor/diode combination to the gate drive (after the gate driver), such that the "on" is delayed, while "off" happens quickly.

This works, but it seems that by having extra turn-on time, the MOSFET is not fully conducting for part of the time (as the voltage goes up), leading to substantially more power dissipation.

Adding delay to the logic (pre gate driver) is simple. Why isn't it always done this way? Why not add the R/D combination on the logic side to do the same thing without all that power loss?

There must be a reason, as almost all of the reference circuits I see show the delay added to the gate drive signal.

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danadak

Joined Mar 10, 2018
4,057
Dead time in modern UP PWMs does not alter the rise/fall time, it simply
delays the pulse so no overlap occurs in the H Bridge causing a shorted
power supply condition. It leaves the Tr and Tf unaffected of the driver
you are using.

Here youc an see that between ph1 and ph2

upload_2019-8-2_16-9-32.png


Regards, Dana.
 

TeeKay6

Joined Apr 20, 2019
572
Dead time in modern UP PWMs does not alter the rise/fall time, it simply
delays the pulse so no overlap occurs in the H Bridge causing a shorted
power supply condition. It leaves the Tr and Tf unaffected of the driver
you are using.

Here youc an see that between ph1 and ph2

View attachment 183069


Regards, Dana.
As I understand the TS, what @danadak describes is what the TS calls "logic delay", and the TS believes it would be advantageous over an analog delay created by slowing down the rise (or fall) time of the gate drive signal. If logic delay is available (not all drivers implement this), then it would likely be the preferred scheme.
 

MisterBill2

Joined Jan 23, 2018
5,738
There is a very big difference between delaying a pulse and slowing the rise time. So not seeing the circuit in question, that is what I can tell you. NEVER slow the rise or fall rate of change if the need is to delay the switching time, They are not equal.
 
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