Does anyone know much about bucket brigade device ICs? I've been trying to simulate a small section of one just to be able to look at various values, and the results don't seem to suggest useable results at the scale these devices are usually made at.

These are the references I've been using:

http://www.electrosmash.com/mn3007-bucket-brigade-devices
http://www.experimentalistsanonymous.com/diy/Datasheets/MN3207.pdf

This is a currently available BBD: http://www.coolaudio.com/docs/datasheet/COOLAUDIO_V3207_DATASHEET.pdf
It's a terrible, terrible datasheet; I've been assuming it's pretty much a straight copy of the MN3207, so just using that datasheet instead.

Here's what I'm seeing:

This simulation of a 10-stage BBD shows attenuation >17dB at the output. I used a 10kHz clock, which is the minimum specified for the MN3207 (and thus creates the longest delay, which is where my interest lies). The summation of the complementary output (point C) is pretty difficult to glean any information from because of the voltage spikes, so the filter output is the best place to look at; I got pretty serious with the output filter, using a 7th order elliptical filter with 60dB minimum attenuation from 5kHz up. The filter has about 7.95dB gain in the passband (<4kHz) when simulated by itself. The filter component values are weird because I made it from a filter design table and didn't bother making them realistic values.

The DC level of the input signal seems to affect the output signal amplitude, and I found a sweet spot for this. Still, the best I can get after only 10 stages is over 17dB attenuation (after taking into account the filter gain).

My question is: if I see that much attenuation after only 10 stages, how do these things have any usable signal level after 1024 or 2048 stages? The MN3207 specifies a maximum +/- 4dB insertion loss. My guess is that the MOSFET parameters in these devices were designed for the application and may be very different from the model I used. Is this correct?

 

I worked on characterizing some of these devices when I was an R&D Tech at HP Labs about 40 years ago; so my recollections will be fuzzy.

The overlap of the clock phases will affect transfer efficiency. I'm not conversant in spice clock specifiers. Could you show how the edges of the two clock phases interact?

Simulating this device using discrete parts is probably not possible because you get much better device matching and coupling when the devices are on the same substrate. You may also get better results if you use devices that have a separate terminal for the bulk connection and vary body bias voltage.

The devices I was working with had no static protection and were operating at voltages much higher than normal (50V).

 

The main issue is that a BBD is not a string of separate MOSFETs in a chain. The gate of one MOSFET physically overlaps the gate of the next such that you effectively have no drain/source region (and hence capacitance) between FETs. This is where your loss is coming from. The overlapping gates drive virtually all of the charge from one FET to the next instead of there being a charge sharing between the source/drain regions on one side of a gate and those on the next.

 

Does anyone know much about bucket brigade device ICs? I've been trying to simulate a small section of one just to be able to look at various values, and the results don't seem to suggest useable results at the scale these devices are usually made at.

These are the references I've been using:

http://www.electrosmash.com/mn3007-bucket-brigade-devices
http://www.experimentalistsanonymous.com/diy/Datasheets/MN3207.pdf

This is a currently available BBD: http://www.coolaudio.com/docs/datasheet/COOLAUDIO_V3207_DATASHEET.pdf
It's a terrible, terrible datasheet; I've been assuming it's pretty much a straight copy of the MN3207, so just using that datasheet instead.

Here's what I'm seeing:

This simulation of a 10-stage BBD shows attenuation >17dB at the output. I used a 10kHz clock, which is the minimum specified for the MN3207 (and thus creates the longest delay, which is where my interest lies). The summation of the complementary output (point C) is pretty difficult to glean any information from because of the voltage spikes, so the filter output is the best place to look at; I got pretty serious with the output filter, using a 7th order elliptical filter with 60dB minimum attenuation from 5kHz up. The filter has about 7.95dB gain in the passband (<4kHz) when simulated by itself. The filter component values are weird because I made it from a filter design table and didn't bother making them realistic values.

The DC level of the input signal seems to affect the output signal amplitude, and I found a sweet spot for this. Still, the best I can get after only 10 stages is over 17dB attenuation (after taking into account the filter gain).

My question is: if I see that much attenuation after only 10 stages, how do these things have any usable signal level after 1024 or 2048 stages? The MN3207 specifies a maximum +/- 4dB insertion loss. My guess is that the MOSFET parameters in these devices were designed for the application and may be very different from the model I used. Is this correct?

View attachment 97776

Practical function? Not any more. Just a long Serial In Serial Out shift register. A memory storage device suitable to drum memories or communication.

 

Practical function? Not any more. Just a long Serial In Serial Out shift register. A memory storage device suitable to drum memories or communication.

It's an analog delay line which is still useful. It's the same technology used in digital cameras (CCDs).

 

Cool, thanks!

The overlap of the clock phases will affect transfer efficiency. I'm not conversant in spice clock specifiers. Could you show how the edges of the two clock phases interact?

Per the datasheet, I gave it a 500ns rise and fall time and tailored the pulse width so that they would cross in both directions at .3Vdd (1.5V).

 

You need to change the FET models so that there very little drain/source capacitance. Depending on the model used, this may or may not be easy to do.

 

It's an analog delay line which is still useful. It's the same technology used in digital cameras (CCDs).

Ah, yes!

 

Let's start with answering some of the questions asked by the TS in the original post.

1. The Coolaudio V3207 is, as stated at the very top of the datasheet, functionally equivalent to the MN3207.
2. The stated insertion loss is "typically" 0dB with a max/min value of +/- 4dB. So in actual operation you will find that the chip works pretty much as advertised with very little loss or gain. Certainly nothing close to the original simulation results of 17dB attenuation after 10 stages
3. The BBD is sensitive to DC offsets at the input, notice that the application circuit for the MN3207 is capacitively coupled at both the input and output.The chip is designed to work with a unipolar power supply.

I certainly am not going to criticize the use of circuit simulation,it's a very valuable tool, but in this case you are trying to guess which FET models to use and no matter what you do you aren't going to get believable results, either pro or con, unless you can find an actual SPICE model of the internal circuitry of an MN3207.

The actual chip works pretty much as advertised and the clock rate that you choose will determine the bandwidth of the output, which is pretty much restricted to relatively low audio frequencies (think Nyquist criteria). It works well for things like flanging, echo delays, etc. If you need more bandwidth use a higher clock frequency and two or more 1024 stage BBDs. Better yet use only one of the longer stage devices.

The actual devices aren't very expensive - why not purchase the minimum quantity and see if they will work in your application? I used some in an audio application many years ago and found that BBD technology worked very well although that circuit and all notes, etc. about the design are lost to the ages.

Regards,
-jp

 

Practical function? Not any more. Just a long Serial In Serial Out shift register. A memory storage device suitable to drum memories or communication.

They were the first semi-decent audio delay lines, used for "springless" reverb units and the like.

 

Hello,

You might be interested in the following PDF.

Bertus

 

Let's start with answering some of the questions asked by the TS in the original post.

I really only asked one question, which WBahn has answered to my satisfaction by confirming my guess that the FET parameters are tailored for the job.

I was able to get a little more signal level out of my simulation by reducing all the available capacitance parameters (Cgd, Cgs, Cjo), but still had quite a bit of attenuation. But my curiosity is satisfied now.

I certainly am not going to criticize the use of circuit simulation,it's a very valuable tool, but in this case you are trying to guess which FET models to use and no matter what you do you aren't going to get believable results, either pro or con, unless you can find an actual SPICE model of the internal circuitry of an MN3207.

I wasn't trying to simulate an MN3207, I was trying to simulate a general BBD circuit so I could look at internal voltages and currents. Just for the hell of it. I don't have an application yet, I just like to see things work for myself, it helps me understand them better.