Hi all,
I'm trying to understand how to calculate the load capacitors for a RTC IC.

I plan on using the MCP7940N RTC IC for a project. One of the crystals that is recommended is: CFS-20632768DZBB. The crystal is rated at CL = 6 pF.

The MCP7940N datasheet has the following equation: CL= (CX1 * CX2)/(CX1 + CX2) + CSTRAY where CX1 is capacitor value on X1 + COSC, CX2 is the capacitor value on CX2 plus COSC, and CSTRAY is PCB stray capacitance.

So, is CL = 6 pF per the crystal datasheet? Is 5 pF a good estimate for CSTRAY for a double sided PCB? How do I estimate COSC?

How do I calculate CX1 and CX2?

Thanks!

 

Welcome to AAC.

This link will help:
https://community.nxp.com/thread/388856

5 pF for CSTRAY is in the middle of the range of 2 to 8 pF. The crystal manufacturer will give you CL. You may need to tune a little after you build. Note that if CX1 = CX2, which is often the case, that equation reduces to (CX+strayC)/2 (i.e., CX^2/2CX = CX/2).

Example:
If your crystal needs a 20 pF load, you will need to put 35pF capacitors at both OSC1 and OSC2: (35+5)/2 = 20 pF . Of course, a 35 pF capacitor will be hard to find, so one might try the next smaller, typical capacitance.

 

Thanks for the reply.

So, the equation becomes: CX1 = CX2 = 2*(CL - CSTRAY). The crystal CL is 6 pF and if CSTRAY is 5 pF, then CX1 = CX2 = 2*(6 - 5) = 2 pF!

Is that correct? It seems like I need no caps or very small ones. If the PCB capacitance is more than 6 pF, the value becomes negative!

Am I wrong?

 

Thanks for the reply.

So, the equation becomes: CX1 = CX2 = 2*(CL - CSTRAY). The crystal CL is 6 pF and if CSTRAY is 5 pF, then CX1 = CX2 = 2*(6 - 5) = 2 pF!

Is that correct? It seems like I need no caps or very small ones. If the PCB capacitance is more than 6 pF, the value becomes negative!

Am I wrong?

Yes, you are wrong. See edit.
Edit2: See post 6

If crystal load (CL) is supposed to be 6 pF and strayC is 5 pF, they add, not subtract. If you rearrange the equation I gave to: CX = 2*CL - strayC , you get CX = 2*6 - 5 = 7 pF each.

Now to check your work, (7 pF + 5 pF)/2 = 6 pF

Edit: Unfortunately, my files have 2 different equations. The link resolves to:
CX = (CL-Cstray)*2, which give a value for each loading capacitor of 2 pF . That seems awfully small. The example I gave was based on the equation posted in PICList (piclist.com). I had not notice that difference until now. I usually used the piclist equation.

TI has a rather exhaustive pdf on the subject. Let me review it and try to get a definitive answer. Will take time.

 

I'm not so sure.

Follow:
CL= (CX1 * CX2)/(CX1 + CX2) + CSTRAY
CL = (CX * CX)/(CX + CX) + CSTRAY <= substitute CX for CX1 and CX2 since they equal each other
CL = (CX^2)/(2CX) + CSTRAY
CL = (CX/2) + CSTRAY
CL - CSTRAY = (CX/2)
2*(CL -CSTRAY) = CX

CX1 = CX2 = 2*(CL-CSTRAY).

 

Source: http://www.ti.com/lit/an/swra372c/swra372c.pdf

In tables at the end of that pdf, a crystal with load of 10 pF requires 12 pF load capacitors, each.

Derivation (assuming C'1 = C'2):

C'x = Cx + Cstray*

Substituting,
CL = (Cx+Cs)^2/ 2(Cx+Cs) = (Cx + Cs)/2

Rearrange,
2*CL = Cx + Cs

Cx = 2*CL -Cs

Cx = 2*6 pF -5 pF = 7 pF each


*Cstray = C parasitic at each pin, hereinafter "Cs"

 

I did a little more searching and found an application note by NXP:

Source: https://www.nxp.com/docs/en/application-note/AN3208.pdf
The value for capacitors C1 and C2 must be chosen so that the series combination: (C1*C2) / (C1+C2) gives
a value close to the load capacitance, CL, specified by the crystal manufacturer. Be sure to add stray
capacitances in the previous calculation. Occasionally, C1 can be chosen to be slightly smaller than C2 to
increase the voltage swing at EXTAL without compromising stability; using a trimmer capacitor in lieu of
C1 or C2 can help find the ideal value.For most applications it is recommended to have the same value for
C1 and C2.

It punts on whether it means added capacitance per pin which add in series (as TI does) or total stray in parallel (as apparently the NXP blog does). I any event, those individual load capacitors are each often a little larger than the datasheet CL value. That is apparent when one looks at tables of recommended capacitors for various crystals.

 

I did a little more searching and found an application note by NXP:

It punts on whether it means added capacitance per pin which add in series (as TI does) or total stray in parallel (as apparently the NXP blog does). I any event, those individual load capacitors are each often a little larger than the datasheet CL value. That is apparent when one looks at tables of recommended capacitors for various crystals.

I've always figured load capacitor values for MCU oscillators pretty much as described in your NXP application note: take the crystal data sheet value for Cl, double it to get a tentative value for the two capacitors, and then subtract a bit (≈ 3-5 pF or so) from those values to get the final capacitor values. Pick a 5% NP0 ceramic capacitor closest to that value, and in nearly all cases you're good to go.

32.768 kHz "watch" crystals are probably a bit trickier (I say "probably" because I've never applied one) due to their low-power drive requirements, but I suspect the principles are the same.

 

So, for a crystal CL of 6 pF, it seems like 7 pF is about right for those 2 caps.

 

@OBW0549
Actually, one can easily argue that the TI, PICList, NXP Blog, and NXP ap. note are all correct. The main difference is how parasitic capacitance is defined. I go with the TI and PICList versions. The NXP Blog is OK if one "simply" changes a parenthesis. The end result is the same, namely, the individual caps end up a little larger than the datasheet value for CL.
@devils4ever
The thing is, you don't want to overload the crystal and you want it to start promptly. Start with something reasonable, and tweak it, if you need the frequency to be more accurate.

 

So, for a crystal CL of 6 pF, it seems like 7 pF is about right for those 2 caps.

Possibly, or maybe a pF or two larger. Microchip application note AN-1365 has some good info, including this:

 

10pF sounds about right for a 6-9pF crystal.
If you want precise timekeeping function, then use a 0-20pF trimmer cap for CX1.

 

So, are larger caps better? Sounds like selecting values is more art than science!

Maybe, I'll purchase both 7 pF and 10 pF and see which works better!

 

Larger is not better. You do not want to overload the crystal and pull it off frequency. Stay close to the manufacturers' recommendations.

 

Choosing crystal load capacitors is neither art nor science. It is more like hit or miss.
Remember, a quartz crystal is a tuning fork. Like an old-school bell, hit it just right to get the right frequency.

 

Choosing crystal load capacitors is neither art nor science. It is more like hit or miss.
Remember, a quartz crystal is a tuning fork. Like an old-school bell, hit it just right to get the right frequency.

This is why I use oscillators to drive my microcontrollers such as ATMEGA328PB!

 

This is why I use oscillators to drive my microcontrollers such as ATMEGA328PB!

That does not stand to reason.

MCUs XTAL pins are designed to be used with quartz crystals. More than a billion devices are in existence that run reliably on quartz crystals directly connected to the MCU XTAL pins.

 

That does not stand to reason.

MCUs XTAL pins are designed to be used with quartz crystals. More than a billion devices are in existence that run reliably on quartz crystals directly connected to the MCU XTAL pins.

Agreed, but I was always leery that I wouldn't get the thing to oscillate. So, I've used oscillators instead.

 

Agreed, but I was always leery that I wouldn't get the thing to oscillate. So, I've used oscillators instead.

You don't need to worry about that; these circuits want to oscillate, and provided you pick a reasonable value for the crystal load capacitors-- and the choice is not especially critical-- they will do so reliably and at the correct frequency.

 

I have always followed manufacturers' recommendations, usually 6pF for 8MHz crystal and have never experienced the oscillator not working properly.