Hi,
I'm new in hardware design. I had to design a 35 cm long bus with 15 connectors for other boards sharing the bus.
The pcb is made up of 8 layers:
- Top: VCC(+5V)
- LAY2: signals
- LAY3: GND
- LAY4: signals
- LAY5: GND
- LAY6: signals
- LAY7: GND
- Bottom: VCC(+5V)

The signals in each layer are 35 cm long and all parallel traces. The traces have a width of 0.30mm and 2.54 mm apart.
I measured crosstalk in signals of the LAY 6 when I excited signal of LAY 2 with oscilloscope.
I expected tha ground planes isolated the signals.
How is this possible?
Thanks,

Bryan

 

Welcome to AAC!

That is a good question and frankly, I don't have an answer.

What are the voltage, current and frequency of the driving signals?
How are your lines terminated?

 

Hi,
I'm new in hardware design. I had to design a 35 cm long bus with 15 connectors for other boards sharing the bus.
The pcb is made up of 8 layers:
- Top: VCC(+5V)
- LAY2: signals
- LAY3: GND
- LAY4: signals
- LAY5: GND
- LAY6: signals
- LAY7: GND
- Bottom: VCC(+5V)

The signals in each layer are 35 cm long and all parallel traces. The traces have a width of 0.30mm and 2.54 mm apart.
I measured crosstalk in signals of the LAY 6 when I excited signal of LAY 2 with oscilloscope.
I expected tha ground planes isolated the signals.
How is this possible?
Thanks,

Bryan

Are the ground planes actually connected to ground?

 

Your post is a little unclear. How is what possible? Have you measured crosstalk and are wondering why?

 

had to design a 35 cm long bus

measured crosstalk

(can you be more specific please - about the physical alignment of those 15 connectors)
? Was the L6 powered
( https://www.google.com/search?q="capacitive+coupling"+"multilayer+pcb" )

 

I'd like to see the scope plot
with two traces on it, the aggressor and the victim, with the scope clips on the probes connected to the ground of the PCB
also a picture of the setup please

Scopes being high impedance inputs are good at "not telling you what you think they are"

 

Welcome to AAC!

The signals in each layer are 35 cm long and all parallel traces. The traces have a width of 0.30mm and 2.54 mm apart.
I measured crosstalk in signals of the LAY 6 when I excited signal of LAY 2 with oscilloscope.

Are these the only two traces with signals on the board? Is this an 8 layer board that's the standard 0.060" thickness? What is the amplitude and phase relationship between the signals? What is the amplitude of the crosstalk? What is the output impedance of the signal drivers? What is the impedance of the scope probe?

Depending on how the signals are routed in relation to each other and the configuration of the ground planes, you can still get crosstalk.

It would be helpful if you gave us an illustration of the signal traces in question and how many openings have been made in the ground planes.

 

Hi,
I undestand the problem. It's not a crosstalk problem between layers because there are GND planes and dieletrics as insulators.
The problem is the connector between the bus and the boards. It is composed by 96 pins on 3 lines and only the first pin of each raw is connected to GND. Then the return current flows all through those pins and the ground is unstable due to the large amount of return current. It dpes not depend on the frequency but on the rising time of the signal (10 ns). Trying to decrease the rising time, you notice a decrease in noise.
I tried to generate the layer 2 signals at t= 0, the layer 4 signals at t = 12 ns and the layer 6 signals at t = 24 ns to decrease the amount of current flowing at the same time and I got better performance.

In conclusion it is not pbc problem but a construction error because a connector with only 3 GND pins on 96 is used.

Thank you all,

Bryan

 

Hi,
I undestand the problem. It's not a crosstalk problem between layers because there are GND planes and dieletrics as insulators.
The problem is the connector between the bus and the boards. It is composed by 96 pins on 3 lines and only the first pin of each raw is connected to GND. Then the return current flows all through those pins and the ground is unstable due to the large amount of return current. It dpes not depend on the frequency but on the rising time of the signal (10 ns). Trying to decrease the rising time, you notice a decrease in noise.
I tried to generate the layer 2 signals at t= 0, the layer 4 signals at t = 12 ns and the layer 6 signals at t = 24 ns to decrease the amount of current flowing at the same time and I got better performance.

In conclusion it is not pcb problem but a construction error because a connector with only 3 GND pins on 96 is used.

Thank you all,

Bryan

Well found

Oh yes, three ground pins and 93 signal / power is terrible
sack the person that thought of that

VME, that uses the 96 pin DIN 41612 has 9 or ten gnd over the two connectors,
and that was marginal
The later VME64, with the bigger connectors added 20 odd more gnd pins,

Good luck with the re design,
.