I have a task to determine which sequence of situations the following counters are generating,the correct answers are for a) is serial counter which counts down the first condition in both counters are Q1Q0=0, this counter counts as 00,11,10,01,00.For b) the correct answer is synchronized counter which counts up:00,01,10,11,00.I want to know how this conditions are determined because I get different,from the truth table of JK.Also for a) I am a little bit confused because clock is connected to Q0,how will I express that when I am writing state equations?Here are the tasks https://prnt.sc/twz7kk.

 

Asynchronous state-machines are a strange animal where race conditions between state & clock signals need to be considered.
https://www.edn.com/transition-maps-guide-successful-asynchronous-state-machine-design/

But these simple dual flip-flop circuits don't seem to have such problems.

 

I have solved under b) I am just confused for a) when I write the truth table C1=Q0,how will that impact Q1 the following state?

 

a) when I write the truth table C1=Q0

How will it help to write C1=Q0? The next state for Q1 is determined by its J&K inputs, and also by whether it receives a clock pulse (which is determined by the state of Q0 and its J&K inputs)?

 

How will it help to write C1=Q0? The next state for Q1 is determined by its J&K inputs, and also by whether it receives a clock pulse (which is determined by the state of Q0 and its J&K inputs)?

Already solved,thanks.

 

when I write the truth table C1=Q0,how will that impact Q1 the following state?

Already solved,thanks.

Care to post your truth table/solution?

AFAIK, they don't teach a formal method for designing asynchronous counters. I saw a paper by a couple of professors named El Naga where they proposed a formal method. Instead of having 1, 0, and X in the truth table, they had α, β, I, and Φ, representing transitions of 0->1, 1->0, 1->1, and 0->0, respectively. They talked about some method to determine when, and which, outputs should connected to later stages.

 

So when clock is rising edge the both states are negations of previous one,when we have another rising edge of clock the value of Q of the first flip flop is negation,and that impacts the clock of the other flip flop which is zero so Q1 stay at the same position and so on...