Me and a friend were making a project where in v were to produce a composite video signal of PAL(phase alternating line) standards....
v were doing a standard VHDL coding to get d needed waveform and then implement it on hardware...
the coding part v are done with...
v made 2 codes...
one in which the sync pulse and video signal are separate and d other one has combined sync pulse and video signal....
m using the 1st code...
keeping in my all the timing constraints i used 50Mhz as my clock signal and formed d sync pulse and a 3 bit number to get 8 different levels innd video signal(to get 8 different coloured bands)...
software work is done....
d code is correct and needs jus the synthesis...
this is not a concern....
V are now working on the hardware...
after vl b applying this code to d FPGA board, v wil b getting standard TTL output for values of 1 and 0 (i.e. 3.3V and 0 respectively)
V are using seperate sections for both d signals....
setting a resistive nework to get 0 to 0.7 V range for d video signal...
V also set another resistive network to set the value of d sync pulse to 0.3 volt....
NOW comes my concern...
being really out of analog study since long...
V are not able to find d proper circuit to pull down the sync pulse from 0 to 0.3 v to -0.3v to 0 v.....
V did try thinkin of a circuit using opamp but m not too sure..
ALso to combine both the above signals v are plannin to use a summing amplifier....
V need help in confirming our doubts!!!
HOPING TO GET REPLIES SOON!!!
v were doing a standard VHDL coding to get d needed waveform and then implement it on hardware...
the coding part v are done with...
v made 2 codes...
one in which the sync pulse and video signal are separate and d other one has combined sync pulse and video signal....
m using the 1st code...
keeping in my all the timing constraints i used 50Mhz as my clock signal and formed d sync pulse and a 3 bit number to get 8 different levels innd video signal(to get 8 different coloured bands)...
software work is done....
d code is correct and needs jus the synthesis...
this is not a concern....
V are now working on the hardware...
after vl b applying this code to d FPGA board, v wil b getting standard TTL output for values of 1 and 0 (i.e. 3.3V and 0 respectively)
V are using seperate sections for both d signals....
setting a resistive nework to get 0 to 0.7 V range for d video signal...
V also set another resistive network to set the value of d sync pulse to 0.3 volt....
NOW comes my concern...
being really out of analog study since long...
V are not able to find d proper circuit to pull down the sync pulse from 0 to 0.3 v to -0.3v to 0 v.....
V did try thinkin of a circuit using opamp but m not too sure..
ALso to combine both the above signals v are plannin to use a summing amplifier....
V need help in confirming our doubts!!!
HOPING TO GET REPLIES SOON!!!
