I am wondering if anyone knows how to calculate the time taken for the integrator's feedback capacitor C9 to discharge?

The rate of change of a capacitor's voltage, in volts per second, is equal to the current through the capacitor, in amperes, divided by the capacitance in farads.

dV/dT = I/C​

Looking at the simulation, the sawtooth ramp reaches 4.5V, and it discharges to 0V at time of around 3.4us. is there a way to find this time through calculation?

See above. Knowing any three of V, C, I and T, you can calculate the missing quantity.

Also, I would have thought that the FET will have some forward voltage, thus prevents the capacitor from sully discharging ?

I don't know about "forward voltage" but the gate current that occurs whenever U5.1's output is high has certainly got to inject an offset voltage of some sort into the integrator when it's being reset.

A JFET to discharge the integrating capacitor is not the best choice; a MOSFET would be much better because of the lack of gate current, and also because any MOSFET (even a dinky little 2N7000) will discharge the integrating capacitor a lot faster than a JFET.

 

The rate of change of a capacitor's voltage, in volts per second, is equal to the current through the capacitor, in amperes, divided by the capacitance in farads.

dV/dT = I/C​

See above. Knowing any three of V, C, I and T, you can calculate the missing quantity.


I don't know about "forward voltage" but the gate current that occurs whenever U5.1's output is high has certainly got to inject an offset voltage of some sort into the integrator when it's being reset.

A JFET to discharge the integrating capacitor is not the best choice; a MOSFET would be much better because of the lack of gate current, and also because any MOSFET (even a dinky little 2N7000) will discharge the integrating capacitor a lot faster than a JFET.

So how can I caulcate the current at time 5T (nearing 0v), since i know C and Vc . Thanks

C = 1nF
5T = unknown
I = unknown
Vc = 4.5V

Looking at the datasheet for j111 has thrown me off! They way that i initially did it was I tried to find some resistance, as from my knowledge the capacitor will flow through the FET to discharge, which must have some resistance in order for it to do so.

Using Vc = V0 X e^(-t/RC)

I rearranged for t giving



I found a value on the data sheet called Rds(on) which had a resistance of 30ohms, it is the resistance (Vds / Ids) in the linear (triode) region. But this is giving me a much too large value !

 

So how can I caulcate the current at time 5T (nearing 0v), since i know C and Vc .

C = 1nF
5T = unknown
I = unknown
Vc = 4.5V

Well, you only know C and V; that's not enough to arrive at a solution since you don't know T or I. So no calculation is possible until you can supply one or the other.

Using Vc = V0 X e^(-t/RC)

I rearranged for t giving

I found a value on the data sheet called Rds(on) which had a resistance of 30ohms, it is the resistance (Vds / Ids) in the linear (triode) region. But this is giving me a much too large value !

Ummm... why? If C = 1 nF and R = 30Ω, the calculated RC time constant would be 30 nanoseconds, which is much too short-- not too long. The reason you're seeing discharge times of several microseconds instead of a couple of hundred nanoseconds is partly related to the fact that the spec'd Rds(on) of the JFET applies only when Vds is small, and here it's not, so the "effective" resistance is actually much larger. It's also partly due to the non-zero response time (i.e., limited slew rate) of U5.1 which introduces a delay between the rising edge of RAW_SQ and the time the JFET begins to conduct.

If you want better performance, replace the JFET with a MOSFET and replace U5.1 with a fast comparator chip.

 

Well, you only know C and V; that's not enough to arrive at a solution since you don't know T or I. So no calculation is possible until you can supply one or the other.


Ummm... why? If C = 1 nF and R = 30Ω, the calculated RC time constant would be 30 nanoseconds, which is much too short-- not too long. The reason you're seeing discharge times of several microseconds instead of a couple of hundred nanoseconds is partly related to the fact that the spec'd Rds(on) of the JFET applies only when Vds is small, and here it's not, so the "effective" resistance is actually much larger. It's also partly due to the non-zero response time (i.e., limited slew rate) of U5.1 which introduces a delay between the rising edge of RAW_SQ and the time the JFET begins to conduct.


If you want better performance, replace the JFET with a MOSFET and replace U5.1 with a fast comparator chip.

Apologies, but its not a case of improving the discharge time. I am only trying to understand the equation for discharge time, that's all. I really didn't expect it to be this complicated. Is there a theoretical method of calculating Vds, thus the resistance to then show a new value for the time constant ?

 

Apologies, but its not a case of improving the discharge time. I am only trying to understand the equation for discharge time, that's all. I really didn't expect it to be this complicated. Is there a theoretical method of calculating Vds, thus the resistance to then show a new value for the time constant ?

Just my humble opinion, but trying to deal with this kind of problem in terms of "time constant" is a great way to drive yourself nuts because first, the "resistance" is highly non-linear with semiconductor devices, and second there is so much variation from device to device that any calculation would have very limited meaning.

Rds(on) in JFETs is mainly useful in estimating insertion loss when the FET is used as an analog switch, and Rds(on) in power MOSFETs is mainly useful in estimating drain-source voltage drop and consequent power dissipation when switching high-current loads; beyond that, I find it more useful to consult the device characteristic curves.

Some things we can calculate. Other things we can only roughly estimate.