Hi,

I have a question about basic gate logic. In the attached pic, I have a NOR gate truth table (2). I'm trying to duplicate that for the (seemingly similar) gate on (1).

For (1):
A,B,C are signal inputs, and Zout is the outcome of these signals, where 0 = low and 1 = high

For (2):
A,B are signal inputs and Cout is outcome of them.

My question:

Since (2) has it that if either gate is open, then Cout is high, indicating no current flows in the circuit across the gates. I similarly structured the truth table in (1) so that if either branch has an open gate, then no current flows in the circuit across the gates. Thus, I believe, (1) is just a larger NOR gate than (2).

Is the truth table of (1) correct, and is my reasoning rational?

 

Just need some clarification:

1. You use open, high or low to describe inputs. What is confusing is you state “if either gate is open” in example 2, then the output is high. This makes no sense.
2. What do you consider a “gate”? Typically, a gate is a logic module. In places you seem to understand that, but then make the statement “either gate is open”.
3. What do you mean by a gate is open?
4. What do you mean by “across the gates”? In your two examples, each only has one gate. There is no other gate for current to flow between

I’m assuming that you have used “gate” to mean different things. Which makes understanding your problem extremely difficult.

Also, you need to be consistent. It’s either high/low, 0/1, or open/?

 

Hi,

I have a question about basic gate logic. In the attached pic, I have a NOR gate truth table (2). I'm trying to duplicate that for the (seemingly similar) gate on (1).

For (1):
A,B,C are signal inputs, and Zout is the outcome of these signals, where 0 = low and 1 = high

For (2):
A,B are signal inputs and Cout is outcome of them.

My question:

Since (2) has it that if either gate is open, then Cout is high, indicating no current flows in the circuit across the gates. I similarly structured the truth table in (1) so that if either branch has an open gate, then no current flows in the circuit across the gates. Thus, I believe, (1) is just a larger NOR gate than (2).

Is the truth table of (1) correct, and is my reasoning rational?

Ask if your circuit in (1) makes sense. Notice that in (2), there in an innate symmetry -- if we swap the label 'a' and 'b', nothing changes. No input is treated any different from any other input.

But in (1) that is not the case. There appears to be something special about 'a' and 'b' that makes them different from 'c'. Why?

What are the boxes in your schematic that have arrows pointing to them? If they are transistors, then draw them as transistors using the proper symbols for the type (BJT, MOSFET, etc) and flavor (PNP, NPN, NFET, PFET, etc.).

What does it mean for a gate to be open? Current doesn't flow across things, it flows through things. I think this sloppiness is a big part of your conceptual problems -- work on it.

Your description of (2) is very wrong. Assuming (and I should have to make such assumptions about your circuit) that you are using NFETs, The only way for the resistor to pull the output HI is for BOTH pull-down networks to be open-circuited, meaning that both inputs must be LO. THAT is consistent with a NOR function. Your description that the output is HI if EITHER gate is open means that there are three possible combinations of the two input values that would meet that criteria, meaning that three of the rows in your truth table would have a HI output.

You need to develop the ability to ask yourself if your reasoning makes sense by considering things like the above.

 

Since the TS's task was, in part, to determine the correct truth table for (1), please don't just give them the truth table for (1). It not only robs them of the intended learning opportunity, but also leads to them turning in someone else's work (yours) and claiming credit for it as their own.

 

Ok thank you! I now see some of my errors, and yes, I need to learn the terminology better, as I'm just learning this material and combinational digital logic, so I don't know much about MOSFETs yet. I appreciate the feedback. Here's an updated version of what I meant:

A,B,C are switches, in what we're calling it in class as a "switch model of a MOSFET".

When the switches are placed into (1) and (2), they are part of the gate. These switches receive an input, either high "1", or low "0". The switches receive either a 0-1V input, which is a "0", or a 4-5V input, which is a "1".

What I had assumed from (2), the NOR gate, is that if either switch is open, then current would not flow in the circuit, but leading to Cout = 1 if either switch, A or B was open.

(1) looks like a larger version of (2), but since it as well only contains 2 branches, I reasoned that if either branch in (1) contains an open switch, then current doesn't flow in the circuit. Thus for (1), if A, B, or C switches are open, then no current flows, making Zout high. Having said that, I'm curious if my truth table in (1) makes sense and is correct. It does appear correct to me, so I'm interested in learning if my rationale has led me to the correct answer.

 

Ok thank you! I now see some of my errors, and yes, I need to learn the terminology better, as I'm just learning this material and combinational digital logic, so I don't know much about MOSFETs yet. I appreciate the feedback. Here's an updated version of what I meant:

A,B,C are switches, in what we're calling it in class as a "switch model of a MOSFET".

When the switches are placed into (1) and (2), they are part of the gate. These switches receive an input, either high "1", or low "0". The switches receive either a 0-1V input, which is a "0", or a 4-5V input, which is a "1".

What I had assumed from (2), the NOR gate, is that if either switch is open, then current would not flow in the circuit, but leading to Cout = 1 if either switch, A or B was open.

(1) looks like a larger version of (2), but since it as well only contains 2 branches, I reasoned that if either branch in (1) contains an open switch, then current doesn't flow in the circuit. Thus for (1), if A, B, or C switches are open, then no current flows, making Zout high. Having said that, I'm curious if my truth table in (1) makes sense and is correct. It does appear correct to me, so I'm interested in learning if my rationale has led me to the correct answer.

"switch model of a MOSFET" is not quite good enough. Is this MOSFET closed when the gate voltage is HI (an NFET) or when it is LO (a PFET)? They way you are using them (as a pull-down network) implies that they are NFETs, so applying a logic-1 to the gate closes the switch and allows current to flow through it.

You are still making the same mistake regarding (2), so let's look at it closely.

The voltage at the output is equal to the supply voltage (Vs, which I'm assuming is 5 V) minus the voltage drop across the resistor, which in turn is equal to the value of the resistance multiplied by the current flowing through it. If no current is flowing, then the voltage drop across it is zero and the output voltage is 5 V (a logic-1). Another way to think of it is that if there is ANY path through the network of switches that connects the output to ground, then (and only then) will the output be 0 V (a logic-0).


So if either switch A or switch is closed (i.e., if either input is a logic-1), the output will be tied to ground giving you a logic-0 at the output. The only way for the output to be a logic-1 is for BOTH switches to be open (i.e., both inputs at a logic-0).

You basic problem is the claim, "if either switch is open, then current would not flow in the circuit." This is like saying that if either door to a room is open that no one can enter the room. If either door is open, then people CAN enter the room using any door that is open. If either switch is CLOSED, then current WILL flow. The only way that current will not flow is if NEITHER switch is CLOSED.

Once you understand that, you can apply the reasoning to the logic table for circuit (1). Look at each of the possible paths leading from the output to ground. Along each path which combinations of inputs will result in there being a complete path to ground? The corresponding rows in the truth table then have a logic-0 output. After doing this for each branch, the remaining rows represent input conditions for which NO path to ground is available and, for those, the resistor pulls the output up to a logic-1.

 

Ok, great feedback. I think I see some mistakes on my truth table for 1, and my terminology needs adjustment. Here goes try 3:

I'm using switch logic such that if the switch voltage is HIGH, it means the switch is closed, so it's a logic-1. Otherwise, it's LOW, and switch logic is logic-0 and the switch is open.

I also realized from your comments that if any switch has logic-1, then the output is 0, since current does flow through that branch, as the switch is effectively a wire. (I was thinking of this as switches in series with Vs, but that's incorrect.)

Using this, I changed my truth table in (1) where if either A or B is open, AND if C is open, then Zout = 1, since current does not flow in these cases.

I think this is correct...?

 

Ok, great feedback. I think I see some mistakes on my truth table for 1, and my terminology needs adjustment. Here goes try 3:

I'm using switch logic such that if the switch voltage is HIGH, it means the switch is closed, so it's a logic-1. Otherwise, it's LOW, and switch logic is logic-0 and the switch is open.

I also realized from your comments that if any switch has logic-1, then the output is 0, since current does flow through that branch, as the switch is effectively a wire. (I was thinking of this as switches in series with Vs, but that's incorrect.)

Using this, I changed my truth table in (1) where if either A or B is open, AND if C is open, then Zout = 1, since current does not flow in these cases.

I think this is correct...?

That is correct.

As another member suggested earlier, it will help if you put your truth table rows in a systematic order -- usually binary ordering is used unless there's a reason to do it another way (gray code is probably the most common alternate).

Let's turn the schematic into a Boolean expression.

The function, let's call it F, is False (making F' True) under the following condition:

F' = (A and B) or C = A·B + C

If we invert this using DeMorgan's Theorem, we get an expression for F

F = ((A·B)')·(C') = (A' + B')·C'

Now compare this to your statement that "if either A or B is open, AND if C is open, then Zout = 1" and you can see that they agree.