Hello,

1.What does a X nm-CMOS technology/process mean? For example, a 180nm CMOS technology only mean that the minimum channel length is 180nm?
2.Which are the informations we get by knowing the technology and what differnetiates the technologies ?

Thank you

 

1.What does a X nm-CMOS technology/process mean? For example, a 180nm CMOS technology only mean that the minimum channel length is 180nm?

That's the general understanding, but it isn't used consistently between manufacturers. Because of that, the leakage and speed figures of merit are more important than feature size.

2.Which are the informations we get by knowing the technology and what differnetiates the technologies ?

That information is Top Secret. Foundries have to give that information to customers. Intel will disclose process information for foundry processes, but the process used for internal projects is only released externally in rare and controlled circumstances.

 

That's the general understanding, but it isn't used consistently between manufacturers. Because of that, the leakage and speed figures of merit are more important than feature size.
That information is Top Secret. Foundries have to give that information to customers. Intel will disclose process information for foundry processes, but the process used for internal projects is only released externally in rare and controlled circumstances.

Sorry my english is bad and I didn't explain exactly what i wanted to ask . By saying "informations" , I mean what does the designer understand about the design. He knows that the minimum length is X nm . Is there any other rule ? For example longer channels must be a multiple of X nm or something like that?

 

A transistor has several design rules for physical layout. In addition to minimum channel length, there may also be a maximum. Width will also have a minimum and maximum length. There will also be rules for width reduction on parallel devices. It's all very process specific.

For example longer channels must be a multiple of X nm or something like that?

In the 180nm node, there were fewer restrictions on device widths and lengths. At smaller geometries, litho limited the number of allowable width and length combinations.

 

A transistor has several design rules for physical layout. In addition to minimum channel length, there may also be a maximum. Width will also have a minimum and maximum length. There will also be rules for width reduction on parallel devices. It's all very process specific.

In the 180nm node, there were fewer restrictions on device widths and lengths. At smaller geometries, litho limited the number of allowable width and length combinations.

Ok Thank you very much!!!

 

Your question got me to thinking about when strained silicon was implemented. I think it was the next node after 180... Details are getting fuzzy because it's been so long since I used it.