Hello,

I was trying to build Clapp oscillator with a JFET (J310) as it is shown in the figure.

Capacitor C is variable and goes from 20 pF to 285 pF. I have connected C3 in series to get suitable equivalent capacitance. With the given values I should get frequencies between 800 kHz and 2 MHz. The simulation confirms this.

However, the circuit on the bench does not behaves as in the simulation. With C = 285 pF I get about 800 kHz with about 3.6 Vpp. Once I start to decrease C the output amplitude starts to decrease and at about 1.5 MHz the oscillator stops. Shouldn't the amplitude be approximately constant as it is in the simulation? Why it decreases? Does the transistor gain goes down and why?


I have tried with a breadboard and with a PCB (Manhattan style) and the results are the same.

Best regards,

Mirko

 

The transistor's gain is probably not the thing that is changing. It might be that C1 and C2 are shunting too much of the tank's energy to ground. One solution might be to decrease C1 and C2, another possible solution is to use a higher Q inductor for L. These are only guesses.

 

Have you tried adding in any parasitic capacitances/inductances/resistances to the sim to see if it matches reality better?

 

Hello,

The schematic in the wiki shows a higher drain resistor:
https://commons.wikimedia.org/wiki/File:ElectronicOscillator_Clapp-JFET-D.svg

Bertus

 

The Clapp (an improvement on the Colpitts) it meant to NOT vary the C1, C2 ratio.

You should use C to vary frequency.

Edit: Pardon my post. I misread something somewhere.

 

I would agree with bertus.......all I see have a higher resistance. And I am with Dick on losing feedback at higher frequencies.

Try a choke in the supply, it might help restore that feedback. I would want some impediment to ac in supply line anyway.

 

Hello,

An other thing to consider is the decoupling:
Decoupling or Bypass Capacitors, Why?

Bertus

 

Remember, the simulation uses ideal components with no parasitic elements, thus the tank circuit has infinite Q, etc.
Your actual circuit does not.

 

Remember, the simulation uses ideal components with no parasitic elements, thus the tank circuit has infinite Q, etc.
Your actual circuit does not.

In an actual device the gate-source cutoff voltage can be as much as 6.5 volts. This means that the FET may not work 0n a 5 volt power supply. Try a higher power supply voltage and see what happens. (A 9-volt battery should be good enough voltage for a test).

 

The transistor's gain is probably not the thing that is changing. It might be that C1 and C2 are shunting too much of the tank's energy to ground. One solution might be to decrease C1 and C2, another possible solution is to use a higher Q inductor for L. These are only guesses.

Bingo.

 

Bingo.

Yes, it must be bingo.

As DickCappels pointed out C1 and C2 are too big. I have found detailed explanation at http://www.rfcafe.com/references/qst/clapp-oscillator-february-1953-qst.htm

Unfortunately I'm not able to test the circuit until monday morning. But I'm confident that your suggestions are right. Thank you for your help. I didn't expected so many quick replies.

 

Hello,

The schematic in the wiki shows a higher drain resistor:
https://commons.wikimedia.org/wiki/File:ElectronicOscillator_Clapp-JFET-D.svg

Bertus

I have tried that, but does not help. This is the solution:

The transistor's gain is probably not the thing that is changing. It might be that C1 and C2 are shunting too much of the tank's energy to ground. One solution might be to decrease C1 and C2, another possible solution is to use a higher Q inductor for L. These are only guesses.

 

Have you tried adding in any parasitic capacitances/inductances/resistances to the sim to see if it matches reality better?

You were right. I selected an inductor from LTspice database with parasitic parameters and the simulation gave dying oscillations as the real circuit. The solution is this one:

Bingo.