Hi,

I have a RTL code.
At first, I synthesized the circuit at 10 ns and run post-synthesis simulation. The circuit worked well.
After that, I changed the timing constraint to 7 ns and re-synthesized the code using:

compile_ultra -retime

DC reported that the circuit has met timing requirements (slack = 0) and there is no design rule violation either. However, the netlist couldn't pass post-synthesis simulation. Does anyone know why?

 

hi k,
Welcome to AAC.
Which synthesiser are you using.?
Please post the circuit.
E

 

Hi Eric,

I used design compiler (Synopsys) ...
below are the tcl script and the constraints:





Do u mean the gate-level diagram?


The RTL code is as attached.

Kung