Hello!
I am designing a circuit to refresh a bootstrap capacitor that is hanging on a slewing node. My issue is that i can't understand the current waveform when the node start to ramp with a constant slew rate dV/dt and what is the theory behind it that can explain this behavior. I will attach files with the part of the circuit, the specs of the node in question and the waveforms from cadence.

 

I can´t see anything in that screenshot. What and where are you measuring?

 

I will give imgur links so you can have a better image quality.
What i am measuring in light green (3rd row) is the current through the capacitor, in bright green (2nd row) is the waveform of the slewing node and you can discard the other waves.
To clarify, the power MOS is a 80V nchannel DMOS with the source connected to 1.8V and the drain connected to BST (one of the capacitor teminals). Its driver is designed to bring his gate to 3.6V to switch on the mos and the slewing node is LX.
Those are the images of the part of the circuit (https://imgur.com/7rQ16Lv), the specs of the node in question (https://imgur.com/89Mi6DH) and the waveforms from cadence (https://imgur.com/PwQAX2p)

 

Can you show the voltage at BST?

 

Sure https://imgur.com/WaZow2h
I also plot the graphs in a more comprehensive way (i hope)
First and second rows are LX and BST, third row is BST-LX and fourth row is current of the capacitor.
So i will try to explain better what is happening. The circuit should charge the capacitor to 1.8V (source of the DMOS) when LX is low (the logic that regulates the signals doesn't matter for this question). The problem is that when LX (bottom node of the cap) ramps up from 0V to 80V, i have an inrush current in the capacitor with that waveform. My issue is that i don't know how to explain and justify this behavior and wave form with the theory. So the problem can be summarized to one simple question: what happens to the current profile when a capacitor is experiencing a ramping voltage at one of his ends? (The other end, BST, is floating/high impedance when this is happening)

 

what happens to the current profile when a capacitor is experiencing a ramping voltage at one of his ends?

The current will be constant with ideal components.
The peak is weird, if it was just the left one I would guess parasitic capacitance or reverse recovery of the mosfet, but the other peak is reversed, so it has to be something else, something that causes the fet to conduct more current at that specific point.
I would check if the 1.8V rail is stable, and find out where that current leaves the fet, the fet symbol looks confusing.

 

Yes, that's why i am wondering what is happening. I would expect a "box" of current of C*dV/dt.
After changing the type of signal from "ideal" to real the peak disappeared and the profile now looks how it should. I think the problem was the sudden change in derivative of the node that led to a spike in current and the "smoothing" is probably due to parasitics of the MOS.
The 1.8V rail was an ideal vdc and the MOS symbol is just a normal fet with a second gate shorted to the source for testing purposes of the fabs.