The difference is negligible. But the load voltage remains nearly same whether we apply a 200V or a 600V.

 

hi SS3,
I would recommend you rethink the design, this version IMO is not a viable solution.
E

 

Hi! I was able to have a waveform across load resistance. I did some changes in the control panel of ltspice. I changed the solver from normal to alternate (in the control panel, go to SPICE tab. There find the engine section). I am sharing the file. However, there is a problem in the circuit. The gate of M1 receives a waveform of ~400V. I am also uploading the 4 pin mosfet (C3M0030090K) (library file for 4 pin mosfet attached). Please change the .lib statement.
Please suggest some edits in the circuit.(@ericgibbs @bertus @ci139 Please see the circuit)
Thanks

 

i'm just "ticking forward" by steps : related data :

• AN-5073 • Active Miller Clamp Technology • Summary
• C3M0030090K • Silicon Carbide Power MOSFET
• 600 V Cool MOS™ C7 Design Guide
• CoolMOS™ C7: Mastering the Art of Quickness. A Technology Description and Design Guide
• CoolMOS C7 650V Switch in a Kelvin Source Configuration
• Advantage of the use of an added driver source lead in discrete Power MOSFETs
  
• ...

I only know Spice - not the chips you are using :: ? is the driver capable of driving the MOSFET - if so then power to driver + driver to mosfet wiring (takes some time for me to figure a out / verify) ... e.g. are you sure it's the way it should be ?? → the "Gate ~ Kelvin-source Voltages" and channel resistances → just ran it -- i guess it'd be worth to try to run single driver (in simple/basic configuration) - in order to find out it's Spice-behaviour ...

... otherwise you plot the COM against reference ground = if your Fets are switching you see the waform it plots on your screenshot there = it's likely what there sould be

 

hi,
Repeating an earlier post, the lower MOSFET is making no contribution to switching the current thru the R7 load.
Which means the lower half of the circuit is redundant.
IMHO there is no point in continuing with the design configured in this way.
E

Update:
To demonstrate the redundancy, this is the sim with bottom section of the circuit deleted, the R7 output is unchanged.!

 

the lower half of the circuit is redundant.
IMHO there is no point in continuing with the design configured in this way.

yes, but as soon as he places the other end of the resistor to capacitive divider (which we hope won't blow) the lower one comes active ...
-----------
the point here is to get KS-SiC-MosFET to run with particular driver ← Which according to datasheet Should be doable "It is suitable for driving IGBTs and power MOSFETs used in motor control and inverter applications."

the control pin VE (iGBT emitter) -- there is no wiring examples for 4-lead MOSFET -- as far as i've reached with it -- it's quite uncertain how the wiring for mosfet goes ...
(+ the opto isolation is not utilized in the test circuit under revision - it's my first time with such - someone could drop a note whether it's OK to go so )

also i run in live log mode assuming Siddharth Singh 3 would be faster than me ...

... i did ?something? -- got the current up but not sure if it's by right causes ((woudn't it be stupid to set current by a capacitor ??? insane . . . must've got it wrong . . . ))
+ striking the Esc 4x -- skips the initial circuit analysis (& starts running the time transition)

 

Hi! Thank you all for your time and hardwork... I ran the simulation and got the results. Uploading them here. new_config.jpg is the plot of load resistance (r7).

The other plots are as follows:-
Blue plot is between gate and ks of mosfet2
Black plot is between gate and ks of mosfet1


Hope this is how the circuit works (This is what I expected from the circuit to work)....
Thank you

 

Which means the lower half of the circuit is redundant.

↑ Please do yourself a favour and plot the current through R7 () . . .

. . . it is good you keep presistent . . . but you are not likely finished with it (consult your teacher and/or classmates)

 

You are in a difficult situation here because

1. The simulation involves High Power , High Currents and High Voltages
2. The simulation has fast switching and transition times
3. The simulation is relatively complex
4. You likely have little spice experience
5. You likely are not familiar with the devices used in the simulation

On the other hand

1. ↑ This is an IDEAL environment setup to learn a lot efficiently ↑
2. If there were a less complex task to conquer it wouldn't introduce you all the exceptional situations that can occur in spice

SUM -- realize that you can not demand yourself succeeding without a considerable effort put to this

• ask more questions more frequently
• work through the datasheets
• see similar circuits www/library/textbooks
• read related application notes
• repeatedly run consistency-/error - checks of your work until you feel there is no questionable nuances remaining

 

plot the current through R7 ()

Here is the plot of I(R7)

 

actually you can plot all sorts of parameters and the functions of these parameters as arguments against the time or any other simulation parameter (... what i haven't tried yet is plotting values against the function ← but this can be achieved by using a behavioural voltage src. with the particular fn. defining the voltage value and later use that voltage to plot parameters against )

so you can also put the drain currents there by (cliking on the drain terminal of a MOSFET ← might be tricky if there are elements nearby or some component connected to drain without a wire -- the status bar shows on what the cursor currently is -- if it's Ix( U3 : D ) -- it's likely the upper mosfets drain terminal's current . . . also available by right clicking the plot panel and selecting "Add Traces" )

/// ... and ... if you also plot the drain current of the Lower MOSFET -- it'll show all near 0 values -- e.g. it is been driven but it changes only the potential difference of GND and COM . . . with no signifficant current passed if your R7's opposite end is connected to GND = if ←such TEST is "ok" with you -- there are no issues - versus - if there should be a simulation of some slightly different circuit - then the trouble is not over yet . . .

. . . including avoiding getting the mosfets conducting at the same time or switching slow ... etc. ...

 

?

/// the master problem is to deliver required power to a particular load -- https://www.eetimes.com/document.asp?doc_id=1278907# (https://en.wikipedia.org/wiki/HVDC_converter) ((← if it is the case)). . . if you do not provide/specify a "functionally complete" circuit -- the members here can not guess what and how to achieve
_________________
. . . that said -- there is an option in Spice to use voltage controlled switch (http://ltwiki.org/index.php?title=S_Voltage_Controlled_Switch) -- which enables you to replace "stubborn" MOSFETS and their drivers with (usually) more reliable elements (for prinipial simulation) -- so if your "prinipial simulation" runs you (if it's required) can start to figure out how to verify the operation of such circuit with particular component models . . .

 

I was able to drive the mosfet alone (in boost converter circuit)

sorry i missed / forgot that - you have already conducted a simple setup test

This is my expected result.

↑↑ if the upper leg of the bridge is closed the voltage would be near zero at R7 even without the lower leg (i hate principial unexplained schematics) -- the author (most probably assumed some active load Z there . . . and ?for noting? that the other end has an electrical ~AC --and/or-- DC pathway to GND drawed the connection . . .) e.g. ← it definitely is an "expected result" but a very very very ... (turn the page)
______
... (a next page) very very very general such
____________________

+ a simplified principial model of the circuit (the simulation speed difference - is why to use such..)
+ a bad guess of the sine inverter . . . but it does something -- (i don't have the equipment nor the experience required nor the urgent need - to verify such designs)
about last : Google → PDF