Hello,
How to calculate the number of (CMOS inverter) buffer stages to drive capacitive load? In my case, I am driving a 1nF capacitive load with CMOS (inverter) buffer with the digital signal having an amplitude of 0-5V, and 1Mhz frequency.

Thanks.

 

You want to compute the voltage on a capacitor of 1nF given an amount of drive current for a given time.

\( V\;=\;\cfrac{1}{C}(I\times\Delta t) \)

For example if you want to have a voltage of 5 Volts in 200 nsec then you need 250 mA

\( I\;=\;(5\text{ V})(10\text{ nf})/(200\text{ ns})\;=\;250\text{ mA} \)

 

Hello,
How to calculate the number of (CMOS inverter) buffer stages to drive capacitive load? In my case, I am driving a 1nF capacitive load with CMOS (inverter) buffer with the digital signal having an amplitude of 0-5V, and 1Mhz frequency.

Thanks.

Basicaly
dont use CMOS logic to drive that sort of load / frequency

 

dont use CMOS logic to drive that sort of load / frequency

That's an interesting blanket statement.
Why?

 

That's an interesting blanket statement.
Why?

@crutscow , you ask "why blanket statement"

Well my thoughts are
the user is evidently not an expert , else they would not be asking

there are many types of CMOS logic Buffers,
some which are better than others at being combined in parallel

Driving 250 mA as expressed by @Papabravo ,
was with a 200 ns rise time,
most CMOS logic , is going to switch faster than this, thus increasing the current proportionately

some CMOS buffers make great little analog amps
which if not careful, the user to keep 200 ns rise time could end up using,
in which case, the high gain of the chip is likely to sauce the thing to oscillate

CMOS having such a high edge speed, is whilst driving a highly capacitive load.
is very liable to over / under shoot,
which could well be disastrous to the load or the driver

Paralleling up drivers , possibly in multiple packages,
has potential to be wired / decoupled "less than ideal"
especially considering the high drive capacitance capability

All of the above are "possible to design around"
but my assumption from the basis of the question "tone"
is that the user is no expert, so will not know these potential problems

Hence ,
my suggestion to not use CMOS buffers in parallel

There are proper high capacitance drive rated buffers around
Im hoping the OP will have look for said

if not I am certain they will be back for suggestions,

Does that answer your question @crutschow ?

 

Just an offhand guess ......
Try this ......

 

Does that answer your question @crutschow ?

Yes.