Glad you figured it out and thanks for letting us know.

I cascaded my circuit to 17 bits for fun. It required 42 of the blocks I made.

Hello, Would you mind sharing the 17bits cascaded solution, or any hint please?

Moderator edit: New thread created from this old thread.

 

Hello, Would you mind sharing the 17bits cascaded solution, or any hint please?

Is this for schoolwork?

 

Is this for schoolwork?

Hello, sorry for the late reply, i got lost trying to find this as well. And to answer your question, it's for one of the CEP's given to us in the semester, schoolwork in a sense yes. Unfortunately, it's due in two days and I am unable to understand the solution as well. So any advice is appreciated. I just need to display the output of an 8-bit unsigned multiplier.
And, as to why it is late, because it was given just in the last week as well.
In short, Respectable senior, any help on how to convert this binary to decimal and finally to a seven segment display. And then I can move n towards the remaining daunting CEPs.
Yours Sincerely
Shah Jan

 

I just need to display the output of an 8-bit unsigned multiplier.
And, as to why it is late, because it was given just in the last week as well.

Are you simulating this? Are you supposed to learn how to do it using the double dabble algorithm?

The 74185 datasheet will give you some clues how to cascade logic that implements double dabble.

 

The 74185 datasheet will give you some clues how to cascade logic that implements double dabble.

Are you simulating this? Are you supposed to learn how to do it using the double dabble algorithm?

The 74185 datasheet will give you some clues how to cascade logic that implements double dabble.

No, not exactly, but now that I look at the datasheet it seems to be very much useful. I have Outputs S0-S15, which are the results of multiplication of any two 8-bit numbers. This multiplication is unsigned and uses 7483, a FA ICs and a half adder circuit made using 7486 and 7408. The display I get can be fed into a 7-segement display directly, but it overflows, after 0-9 and then cannot display 10-15.

 

Are you simulating this? Are you supposed to learn how to do it using the double dabble algorithm?

The 74185 datasheet will give you some clues how to cascade logic that implements double dabble.

My question along with my thanks, senior is can I directly use this IC.
I am simulating all this in Proteus.
Actually, this is the problem I'm facing, how do I connect the outputs even if I use a similar IC. What I have is a 16 bit output essentially that is not displaying correctly.
Here is what I have made, its messy and not that great, but if you just want to get an idea about the question
And it contains the solution one of the other respectable persons made.

 

My question along with my thanks, senior is can I directly use this IC.
I am simulating all this in Proteus.

74185 is no longer available.

Proteus has a symbol for 74185, but it doesn't work for simulations.

You can implement a 4 bit double dabble with about 18 gates. Information is readily available on the internet.

I read this once and believe it's correct: https://en.wikipedia.org/wiki/Double_dabble

Fortunately for you, 2 days is enough time to do it.

 

74185 is no longer available.

Proteus has a symbol for 74185, but it doesn't work for simulations.

You can implement a 4 bit double dabble with about 18 gates. Information is readily available on the internet.

I read this once and believe it's correct: https://en.wikipedia.org/wiki/Double_dabble

Fortunately for you, 2 days is enough time to do it.

ok then I'm on it. Thanks