So what you want to be doing is working in bank 0 with the variables and switching when you need to go to other banks and then switch back to bank 0 again.

For example in my code the Init routine should end ike this

movlb   0
return

Is my understand of this now correct? I am now going to incorporate your optimising code suggestions which by looking at I can see you are able to avoid switching banks too often by carefully choosing which routine uses which bank.

Thank you for the help I have learnt a lot in these last few days.

Regards,

pic122

I didn't mean to imply that you are doing anything incorrectly. I just wanted you to be aware of banking errors.

Have fun. Cheerful regards, Mike

 

I just wanted you to be aware of banking errors.

Yes I think later down the line that would have caused me trouble. Thanks for letting me know. Regards, pic122.

 

If you're interested, here's a simple fixed delay subsystem (for 14-bit core devices) that provides precise "cycle accurate" delays using almost any clock. Just keep in mind that the range of delays is 11..327690 cycles. That's 11..327690 usecs with a 4-MHz clock, or 6..163845 usecs with an 8-MHz clock, etc.

Regards, Mike

        cblock 0x20
delayHi
        endc

;******************************************************************
;  K8LH DelayCy() subsystem macro generates four instructions	  *
;******************************************************************
        radix   dec
clock   equ     4               ; 4, 8, 12, 16, 20 (MHz), etc.
usecs   equ     clock/4         ; cycles/microsecond multiplier
msecs   equ     clock/4*1000    ; cycles/millisecond multiplier

DelayCy macro   delay           ; 11..327690 cycle range
        movlw   high((delay-11)/5)+1
        movwf   delayhi
        movlw   low ((delay-11)/5)
        call    uDelay-((delay-11)%5)
        endm

;******************************************************************
;  example code for simulation testing with stopwatch             *
;******************************************************************
        org     0x000
SimTest
        DelayCy(200*usecs)      ; <- put simulator PC here
        goto    $               ; <- put simulator break point here

;******************************************************************
;  K8LH DelayCy() subsystem uDelay subroutine                     *
;******************************************************************
        nop                     ; entry for (delay-11)%5 == 4     |00
        nop                     ; entry for (delay-11)%5 == 3     |00
        nop                     ; entry for (delay-11)%5 == 2     |00
        nop                     ; entry for (delay-11)%5 == 1     |00
uDelay  addlw   -1              ; subtract 5 cycle loop time      |00
        skpc                    ; borrow? no, skip, else          |00
        decfsz  delayhi,F       ; done?  yes, skip, else          |00
        goto    uDelay          ; do another loop                 |00
        return                  ;                                 |00

;******************************************************************
        end

 

If you're interested, here's a simple fixed delay subsystem (for 14-bit core devices) that provides precise "cycle accurate" delays using almost any clock.

Very interested thanks.