If in another case.
Input:
D4D3D2D1
1011
B2B1
11 - ADD
B4B3
Register 2 - 10
B6B5
Register 3 - 11
Result
0 + 1 = 1
No carry.

Is this what you're to get at ?
But when will i be using the carry ? Is what im saying is right ?

You will use carry when you have binary 1+1.
Binary 1+1=10. The 0 is the result. The 1 is the carry bit.

 

But how do you make it to work ?
Is what i wrote earlier a working example ?
Like , is that what the question is asking for it to do ?

Based on Shteii01 description, let be draw a simple block diagram for you that may help you understand better.

The ALU will perform 4 functions NOR, AND, NAND and ADD. It is controlled by B1 & B2 through a 2 to 4bit decoder. The Black box is sitting between the DATA REGISTER (input) and the ALU. You have to figure out how to design so it can only select one data bit at a time to go into the ALU. What is inside the ALU is up to you to design. But I guess there must be a 2-input NOR gate, a 2-input AND gate, a 2-input NAND gate and a full adder.

I hope it is clearer to you now what you're supposed to do.

Mr Chips used "R1 to R4" to represent what Shteii01 used "D1 to D4" to represent the INPUT, but they are really the same thing.

Allen

 

7) If you perform an ADD, you should store the trailing bit in the output register,
and the leading bit in a carry-out register (D-type latch).

Oops... Looks like you dont even need a CarryIn input. Just the carry out is needed when you're adding 1+1=10.

So only a half adder is needed in ALU.

Allen

 

Hello JekasG

Your statement is somewhat confusing for Mi:

1) Four input bits of data, stored in a single-bit register (D-type latch)
These 4 BIT's, which are DATA, will be stored in D-type latch.
No problem with them.

2) One carry-in bit, stored in a register (D-type latch)
This is a carry BIT which almost all adders have; will also be stored in a D-type latch.

3) Six instruction bits, each stored in a register (D-type latch).
Ok. these are 6 BIT's that control the system.
We could name these 6 BIT's as Instruction Register.
More clearly 6 BIT's Instruction Register.
Instruct the system what to do according to their logic state.

Now, Our 6 BIT's Instruction Register is broken down as follows:
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
a. The first and second bits of the instruction (B1 and B2) specify the operation to be performed.
- 00 is a NOR operation
- 01 is a AND operation
- 10 is an NAND operation
- 11 is an ADD operation
This 2 BIT's (B2, B1), instruct the system to perform a logic or an arithmetic function.

My confución starts here:
b. The third and fourth bits of the instruction (B3 and B4) specify one input data register Which Will be used in your calculation.
- Register 0 is addressed as 00
- Register 1 is addressed as 01
- Register 2 is addressed as 10
- Register 3 is addressed as 11.
Ok, they are referring to our 6 BIT's instruction register.
but
Looks that are mentioning what was said here:
1) Four input bits of data, stored in a single-bit register (D-type latch)
Because these 4 BIT's are DATA (Plus Carry-In of course).

Here I also find confusing:
c. The fifth and sixth bits of the instruction (B5 and B6) specify the second input data register Which Will be used in your calculation.
- Register 0 is addressed as 00
- Register 1 is addressed as 01
- Register 2 is addressed as 10
- Register 3 is addressed as 11.
Ok, they are referring to our (6 BIT's instruction register)
but
looks that are mentioning what was said here:
1) Four input bits of data, stored in a single-bit register (D-type latch)
Because these (4 BIT's) are DATA (Plus Carry-In pos course).
What they mean with one input data and second input data ?

It seems that the input bits of data has more than 4 BIT's as mentioned here:
1) Four input bits of data, stored in a single-bit register (D-type latch)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Or, how could I understand this ?

 

my idea would be based on the 74181 arithmetic logic unit.