If 2.4576Mhz is the ADC sample rate. And they are over sampling 64x to create 2.4576Mhz / 64 = 38,000 samples per second per channel. How is this related to the actual signal frequency chosen per channel? For example. Let's make the signal frequency 1024 Hertz per channel. What would be the oversampling rate? would it still be 38,000 samples per second?

And what kind of ADC has 16 channel a 2.4576 Mhz?

 

Let's make the signal frequency 1024 Hertz per channel. What would be the oversampling rate? would it still be 38,000 samples per second?

The oversample rate is 2.4576MHz / 1024 = 2400

And what kind of ADC has 16 channel a 2.4576 Mhz?

Since you came up with those exact, particular frequencies, why not tell us.(?)

 

The oversample rate is 2.4576MHz / 1024 = 2400

If the signal is 2400 Hz, then the sampling is only 1024 Hz which is under sampled and aliasing can result. But if the ADC is 24 Bit. Would it somehow able to compensate for that?

Since you came up with those exact, particular frequencies, why not tell us.(?)

I just saw specs of some EEG amplifier systems. Is there really a chip that can do simultaneous 16 channel EEG measurements? or do they use 3 or more chips?

 

So far, everything that is written makes no sense to me.

If the DAQ system can measure 16 channels, that's great. Now just focus on what happens at one channel.
If your sampling rate is 4800sps, the Nyquist limit is 2400Hz. You must apply an anti-aliasing filter that eliminates all frequencies above the Nyquist limit, i.e. a low pass filter that attenuates everything above 2400Hz.

The number of ADC bits is of no consideration here.

 

So far, everything that is written makes no sense to me.

If the DAQ system can measure 16 channels, that's great. Now just focus on what happens at one channel.
If your sampling rate is 4800sps, the Nyquist limit is 2400Hz. You must apply an anti-aliasing filter that eliminates all frequencies above the Nyquist limit, i.e. a low pass filter that attenuates everything above 2400Hz.

The number of ADC bits is of no consideration here.

The sampling rate of 4800sps is also 4800 Hz? Why call it sps instead of Hertz? But 4800 x 2400 = 11.52Mhz which is above the 2.4576Mhz example I gave.

In system that has 16 channels. Do you have individual 16 ADC chips or one chip with 16 ADC inside? Most cost $15,000 so I wonder what parts are so expensive. is there a chip that cost $5000?

 

What are you asking about?

Oh, you mentioned EEG. searching for: eeg chip

hit: https://www.ti.com/product/ADS1299

ADS1299-x Low-Noise, 4-, 6-, 8-Channel, 24-Bit, Analog-to-Digital Converter for EEG and
Biopotential Measurements

datasheet: https://www.ti.com/lit/ds/symlink/ads1299.pdf

Looks like 8 channels max... But it's about $40/chip so perhaps 2 chips?

 

Hi Gpand,
This PDF covers ADC oversampling, may help you.
E

 

The sampling rate of 4800sps is also 4800 Hz? Why call it sps instead of Hertz? But 4800 x 2400 = 11.52Mhz which is above the 2.4576Mhz example I gave.

In system that has 16 channels. Do you have individual 16 ADC chips or one chip with 16 ADC inside? Most cost $15,000 so I wonder what parts are so expensive. is there a chip that cost $5000?

Why did you multiply 4800 by 2400?
What does that mean?

The value 4800 I chose as an example. You can substitute any value you wish.

 

Here is a spec from the Brainmaster Discovery 20 series:

"... it provides 24-bit conversion with an internal sampling rate of 1024 samples/second and 256 sps data rate to the PC, providing 20 high-resolution and aliasing-free signals.

It has a bandwidth of 0.000 to 60 Hz, providing accurate recording of EEG from DC offset up to gamma and above."

So the clock is 60 Hz x 1024sps = 61,440 kHz, or is it 61,440 x 20 channel = 1.2288 Mhz? How do you device the clock to 20 channels instead of each having 1.2288 Mhz?

And how come it is only 256 sample per second rate to PC from 1024/samples/second internal sampling?

 

Here is a spec from the Brainmaster Discovery 20 series:

"... it provides 24-bit conversion with an internal sampling rate of 1024 samples/second and 256 sps data rate to the PC, providing 20 high-resolution and aliasing-free signals.

It has a bandwidth of 0.000 to 60 Hz, providing accurate recording of EEG from DC offset up to gamma and above."

So the clock is 60 Hz x 1024sps = 61,440 kHz, or is it 61,440 x 20 channel = 1.2288 Mhz? How do you device the clock to 20 channels instead of each having 1.2288 Mhz?

And how come it is only 256 sample per second rate to PC from 1024/samples/second internal sampling?

Your math is meaningless.

The signal bandwidth is 0-60Hz.
The sampling rate is 1024 sps.

Why are you multiplying 60 by 1024?

 

So the clock is 60 Hz x 1024sps = 61,440 kHz, or is it 61,440 x 20 channel = 1.2288 Mhz?

No. That is not the way you wound calculate it.

First you would need to know how many physical ADCs there are. At the low rate of 1024 sps, it is likely a single ADC that switches between the 20 channels giving you an actual conversion rate of 20480 conversions per second, i.e. 20 x 1024.

And each conversion takes multiple clocks of the ADC, probably at least 24 (one per bit) + a few extra, so maybe 30 clocks per conversion.

That would require a clock rate of 30 x 20480 or 614,400 Hz.

 

Your math is meaningless.

The signal bandwidth is 0-60Hz.
The sampling rate is 1024 sps.

Why are you multiplying 60 by 1024?

In the second message. Cruts mentioned that "The oversample rate is 2.4576MHz / 1024 = 2400".

The 1024 is the signal or signal bandwidth 0 - 1024Hz.
The sampling rate is 2400 sps.
So if you multiply 1024Hz by 2400sps = 2.4576Mhz. You arrive at the clock frequency !

Hence in the above, I multiply 60 Hz by 1024 sps to arrive at the clock frequency of 61,440 kHz. What is wrong with that given I just followed an early example?

 

No. That is not the way you wound calculate it.

First you would need to know how many physical ADCs there are. At the low rate of 1024 sps, it is likely a single ADC that switches between the 20 channels giving you an actual conversion rate of 20480 conversions per second, i.e. 20 x 1024.

And each conversion takes multiple clocks of the ADC, probably at least 24 (one per bit) + a few extra, so maybe 30 clocks per conversion.

That would require a clock rate of 30 x 20480 or 614,400 Hz.

How do you apply it to the actual example in message 2 by cruts when he said " "The oversample rate is 2.4576MHz / 1024 = 2400". If you will use your computation. 0 to 64 Hz is the signal range. 38400 Hz is the sampling frequency. So if you multiply 16 channels by 38400 Hz = 614,400Hz. And 30 clocks per conversion (since it's also 24 bit) is 30 x 614,400 Hz = 18.432Mhz ! It's only 2.4576Mhz so your example doesn't seem to tally.

 

It does not matter if the signal frequency is 1Hz, 10Hz, or 100Hz.
The sampling frequency is still the same, 1024 samples per second in the example given.

We do not know your definition of clock frequency. Is this the internal clock of the ADC?
The clock frequency will depend on the architecture of the ADC, flash, SAR, sigma-delta, and the number of bits.

Let us use the example of 1024 sps.
Assuming that there is no time delay caused by switching input channels, 16 channels would require a sampling rate of 1024sps x 16 = 16384 sps.
Now if you want to oversample by 16, 16384sps x 16 = 262144 sps.
This has nothing to do with the ADC clock rate until we know how many clock cycles it takes for each conversion.

(For example, I am running an ADC that samples at 50Msps. I get a new sample on every clock cycle. Hence the ADC clock is 50MHz.)

 

Oh. In my first message. I thought the 2.4576Mhz is the clock. So it is just the sampling rate of the ADC or 2.4576Mega samples /second? So the clock is the combination of all 16 channels which could be in Gigahertz?

 

Oh. In my first message. I thought the 2.4576Mhz is the clock.

You tell us, you wrote it, we didn’t!

It would help if we knew what document you are reading. Please link to it.

I am going to guess thar the 2.4567 MHz is the clock frequency of a processor in the chip and the ADC frequency us probably divided down from that.

 

You made reference to this.
https://brainmaster.com/product/discovery-20-series/

This is what we know as advertised:

The BrainMaster Discovery 20 channel biofeedback device introduces a new price and value point into the world of EEG and QEEG. It is quite simply the most affordable and versatile whole-head EEG, with high-quality clinical grade EEG acquisition and a large range of available software and features. Like its big brother, the Discovery 24E, it provides 24-bit conversion with an internal sampling rate of 1024 samples/second and 256 sps data rate to the PC, providing 20 high-resolution and aliasing-free signals.

It has a bandwidth of 0.000 to 60 Hz, providing accurate recording of EEG from DC offset up to gamma and above. It operates with the full range of BrainMaster 4.0 software, including the BrainAvatar package, as well as compatibility with industry-standard packages such as BrainDX, NewMind, WinEEG, SKIL, EEGLab, NeuroGuide and others. Discovery 20 recordings can be used in virtually all types of analysis, and provide noise-free signals suitable for mapping, Z-Scores, live Z-Score training, and live sLORETA imaging and Z-Scores. With true DC capability, it excels for use in slow-cortical potential (SCP), or Infra-Low Frequency (ILF) or Infra-Slow Fluctuation (ISF) research and clinical practice. The optional impedance-sensing lid is also available, as are optional outputs for photic, auditory, or magnetic stimulation, and an optional event button input.

In summary,
number of channels = 20
number of ADC bits = 24
sampling rate = 1024 samples/second
bandwidth = 0 - 60Hz

There is no mention of clock frequency and it is not relevant at this point.

 

You tell us, you wrote it, we didn’t!

It would help if we knew what document you are reading. Please link to it.

I am going to guess thar the 2.4567 MHz is the clock frequency of a processor in the chip and the ADC frequency us probably divided down from that.

Here for the product description:

"Each of the 16 analog to digital converters operates at 2.4576 MHz. Oversampling 64 times yields the internal sampling rate of 38.400 Hz (per channel and for all channels!). In addition, a powerful floating point Digital Signal Processor performs oversampling and real-time filtering of the biosignal data (between 0 Hz – 2.400 Hz). Therefore, a typical sampling frequency of 256 Hz yields an oversampling rate of 9.600.".

In my original post I wrote. "If 2.4576Mhz is the ADC sample rate. And they are over sampling 64x to create 2.4576Mhz / 64 = 38,000 samples per second per channel. How is this related to the actual signal frequency chosen per channel? For example. Let's make the signal frequency 1024 Hertz per channel. What would be the oversampling rate? would it still be 38,000 samples per second? "

cruts answered:

"The oversample rate is 2.4576MHz / 1024 = 2400."

That's where all my further messages were based on. But if 2.4576Mhz is the clock rate. Then if the signal is 1024 Hz. What is the oversampling rate?

 

Oversampling rate has nothing to do with the input frequency. It does not matter what is the input frequency.

In the example given, assume the biological signal has a range of 0-2.4Hz.

You can select a data frequency of 256 samples/sec after signal averaging.
In effect the ADC is sampling at 2.4576M samples/sec.
Hence the oversampling ratio is 2457600/256 = 9600

In other words the ADC is oversampling by a factor of 64 and the DSP is averaging by a factor of 150.

 

Oversampling rate has nothing to do with the input frequency. It does not matter what is the input frequency.

In the example given, assume the biological signal has a range of 0-2.4Hz.

You can select a data frequency of 256 samples/sec after signal averaging.
In effect the ADC is sampling at 2.4576M samples/sec.
Hence the oversampling ratio is 2457600/256 = 9600

In other words the ADC is oversampling by a factor of 64 and the DSP is averaging by a factor of 150.

When you mentioned "You can select a data frequency of 256 samples/sec after signal averaging.". Did you mean input frequency of 256Hz? If I want input frequency to be 1024Hz. What is the oversampling rate? But is it not the ADC frequency is 2.4576Mhz and you divide 2.4576Mhz by 1024Hz (input frequency) to come up with 2048Hz oversampling?