I'm trying to design a 3 bit signed up_down counter, it will have a clear input-which clears the counter, also set and enable inputs, when it is enabled(1), the set input will control the up or down.
Since this is a signed counter, i need to show underflow and overflow as an output as well.
Its a bit confused me. you have any suggestions to me?

 

Grab a data sheet for a 74191.

 

How do you want to design it? VHDL? Only with FETs...? Logic Gates?

 

How do you want to design it? VHDL? Only with FETs...? Logic Gates?

well thanks, but i designed it.
Is it possible to write the vhdl code and then see the logic diagram of circuit? That sounds quite easy.

 

Is it possible to write the vhdl code and then see the logic diagram of circuit? That sounds quite easy

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Yes it is possible. Xilinx offers the 'ISE WEBpack' download for free. It is a big download, and you will have to sign up with Xilinx and register it.
It is a bit intimidating to get started with, but if you follow the guided tutorials, you will get the hang of it quickly. The nice thing is that this software is everything in one, a development, simulation, and target programmer in one package.

Anyways, have fun!