Hello,

Thought some people here might find this interesting, so here's a tutorial I wrote a few years back (with help and vetting from the NesDev community) on how to read the NMOS circuit displays in Visual 6502. Visual 6502 is a JavaScript-based digital circuit simulation of the 6502 CPU, and more generally a framework for simulating old chips.

The tutorial uses examples from the APU (audio circuitry) and PPU (graphics processor) in the NES. This is probably a good thing, as those circuits are much less dense and so easier to read directly compared to the 6502 circuitry. (The 6502 is a full custom design, while the APU and PPU are mostly built with standard cell components.) The particular examples aren't hugely important, and the principles are exactly the same.

I'm primarily a coder who's dabbled a bit in hardware (or hardware simulated in software anyway), so the tutorial should (hopefully) be easy to read even for people without much electronics experience.

Cheers,
Ulfalizer

 

Nice. Some comments. I think the layout would be easier to read if you didn't use solid colors so you can see what's over or under a layer. You should draw the contacts. Why did you choose to color code the diffusions? I'd prefer texting to derive netnames.

I worked on designs that had 10 layers of metal and about the only layer that was solid fill was contact (for poly, diffusion, and metal1; actually connecting layers that were traditionally done with a single contact layer got more complicated). Even when we only had one layer of metal, non-solid fill patterns were the norm.

 

Nice. Some comments. I think the layout would be easier to read if you didn't use solid colors so you can see what's over or under a layer. You should draw the contacts. Why did you choose to color code the diffusions? I'd prefer texting to derive netnames.

I worked on designs that had 10 layers of metal and about the only layer that was solid fill was contact (for poly, diffusion, and metal1; actually connecting layers that were traditionally done with a single contact layer got more complicated). Even when we only had one layer of metal, non-solid fill patterns were the norm.

Thanks!

As far as I can remember, all the pictures were pulled straight from Visual 6502/2A03/2C02 (with some added labels, obviously). The 2A03 is NES CPU package -- which also has audio, DMA, and misc. support circuitry -- and the 2C02 the PPU. I haven't worked on the simulators personally, so I can't comment on their choices. Visual 6502 seems to use some transparency at least.

I guess the drawings could be tweaked to add some more details.

 

Thanks!

As far as I can remember, all the pictures were pulled straight from Visual 6502/2A03/2C02 (with some added labels, obviously). The 2A03 is NES CPU package -- which also has audio, DMA, and misc. support circuitry -- and the 2C02 the PPU. I haven't worked on the simulators personally, so I can't comment on their choices. Visual 6502 seems to use some transparency at least.

I guess the drawings could be tweaked to add some more details.

The usual way to figure out how things are connected is to click on a node and seeing what gets highlighted by the way, as mentioned in the nodes section. Visual 6502 doesn't explicitly record the locations of buried contacts. Adding them to the figures would make it clearer where there's transistors and where the metal is just "passing over" the polysilicon at least, which I guess is what you have in mind.

 

The usual way to figure out how things are connected is to click on a node and seeing what gets highlighted by the way, as mentioned in the nodes section. Visual 6502 doesn't explicitly record the locations of buried contacts. Adding them to the figures would make it clearer where there's transistors and where the metal is just "passing over" the polysilicon at least, which I guess is what you have in mind.

Urr... scrap that. Metal and poly would never make a transistor anyway, and buried contacts seem to be for when you want a connection between diffusion and poly specifically without making a transistor.

I guess that part could be clarified in e.g. the NOR example, where there's metal passing over poly (though the poly is displayed on top in the simulator). The highlighting hints at how things are connected, but maybe it's unnecessarily subtle.

 

I added a note to clarify that the metal + poly overlap does not form transistors to the NOR example.

 

The usual way to figure out how things are connected is to click on a node and seeing what gets highlighted by the way, as mentioned in the nodes section. Visual 6502 doesn't explicitly record the locations of buried contacts. Adding them to the figures would make it clearer where there's transistors and where the metal is just "passing over" the polysilicon at least, which I guess is what you have in mind.

I spent several decades reading layout, so I don't need any automation to help me trace the nets of simple circuits. And I was looking at the wiki, not using the app. I wouldn't need an app to read simple layout.

It's confusing to look at layout that doesn't show contacts or vias. When poly crosses metal, there's no connection without a contact. That isn't clear from the pictures on the wiki because contacts aren't drawn. For example, the NOR picture with poly crossing metal1 and metal2. But there are instances in that picture where poly is definitely connecting to metal, but contacts aren't shown.

The adder picture looks strange. Sometimes poly is drawn over diffusion and sometimes it's drawn under. Makes me dizzy looking at it. Transparency would make it easier to read...

 

I spent several decades reading layout, so I don't need any automation to help me trace the nets of simple circuits. And I was looking at the wiki, not using the app. I wouldn't need an app to read simple layout.

It was written specifically as a tutorial for (simulators based on) Visual 6502, as people often referenced it on the forums and IRC but few knew how to make sense of it. (I figured it out only after nagging people for long enough on IRC.) I agree that the visualization could be nicer in some ways.

It's confusing to look at layout that doesn't show contacts or vias. When poly crosses metal, there's no connection without a contact. That isn't clear from the pictures on the wiki because contacts aren't drawn. For example, the NOR picture with poly crossing metal1 and metal2. But there are instances in that picture where poly is definitely connecting to metal, but contacts aren't shown.

Yeah, it would probably be nicer if Visual 6502 showed those. I've added a clarification to the NOR section now at least. Maybe more could be said about contacts and vias earlier too.

The adder picture looks strange. Sometimes poly is drawn over diffusion and sometimes it's drawn under. Makes me dizzy looking at it. Transparency would make it easier to read...

The instances where it is drawn above the diffusion is where the transistors are. Not perfectly sure what's going on in the chip itself there.

Thanks for the feedback!

 

The instances where it is drawn above the diffusion is where the transistors are. Not perfectly sure what's going on in the chip itself there.

The poly has to be continuous, otherwise it would have a space from nearby diffusion. That means the rendering algorithm has some random method for determining which color to draw for overlaps.

 

The poly has to be continuous, otherwise it would have a space from nearby diffusion. That means the rendering algorithm has some random method for determining which color to draw for overlaps.

Maybe I'm reading you wrong, but the places where the poly is drawn over the diffusion are the only ones where there's transistors. (Otherwise the adder logic doesn't check out, and it also works in the simulation.)

If you assume that diffusion is drawn over poly and that poly carves out a chunk of the diffusion in the case of transistors, does the visualization make sense then?

Sorry if that's exactly what you meant.

 

In this layout, the red circular regions indicate transistors that don't show poly crossing diffusion. The poly comes in from the right and terminates on the left-most diffusion. Poly can't break "near" or under the diffusion or it will form some weird device. It also appears that the coloring of power diffusion is incorrect; the annotated layout has too much ground and no power...



BTW, what is the source for the layout? From a peel back or from schematics? I didn't read much of the wiki; for the most part, I just looked at the pictures...

 

In this layout, the red circular regions indicate transistors that don't show poly crossing diffusion. The poly comes in from the right and terminates on the left-most diffusion. Poly can't break "near" or under the diffusion or it will form some weird device. It also appears that the coloring of power diffusion is incorrect; the annotated layout has too much ground and no power...

Does the same go for the yellow diffusion, which floats and isn't connected directly to neither power nor ground? There are no transistors modeled at the red circles in the simulator, and having a transistor that opens up between ground (green diffusion) and more ground seems weird. The only transistors that are modeled are where the poly is drawn on top, and that's the only thing that makes sense logic-wise for the function too.

/sum1 out and /carry out have power sources attached to them outside the picture. (The red diffusion can be seen at the edges.) The tutorial simple says that "both /sum1 out and /carry out are powered" at the moment, but maybe a remark could be added there.

BTW, what is the source for the layout? From a peel back or from schematics? I didn't read much of the wiki; for the most part, I just looked at the pictures...

The chips were decapped and a bunch of photographs taken and stitched together. A transistor-level netlist was produced from the photographs, and polygons drawn on top as a visualization. visual6502.org goes over the process, and here's a talk that goes over it too. (Can't remember how much detail the talk goes into besides the basic process though.)

The 6502 simulator itself can be found here by the way. It's preloaded with a simple program.

 

Does the same go for the yellow diffusion, which floats and isn't connected directly to neither power nor ground?

Can't deciper the layout without being able to discern more connectivity. There are a lot of poly/diffusion crossings that are missing. You just can't run poly up to diffusion, gap is required. You can see endcaps on the left most diffusion edge, so poly has to run continuously over the diffusion. I assume this is NMOS layout and that they're using active loads.

I question whether the simulator you refer to is working correctly...

 

Can't deciper the layout without being able to discern more connectivity. There are a lot of poly/diffusion crossings that are missing. You just can't run poly up to diffusion, gap is required. You can see endcaps on the left most diffusion edge, so poly has to run continuously over the diffusion. I assume this is NMOS layout and that they're using active loads.

I question whether the simulator you refer to is working correctly...

I think I verified the function of the adder (which is used to implement frequency sweeps for the pulse channels) back when I first wrote the tutorial. Many other parts of the simulation have been verified at least.

Maybe the problem is only with the visualization itself. Everything makes sense from a boolean perspective if you assume polysilicon is "allowed to" pass over diffusion like that.

For reference, here's the same part of the adder with some additional context and the lowest polysilicon trace highlighted to show that it goes all the way from right to left. I also added blue dots where the transistors are.



If you want to look at the original die shots, you can find them here. For reference, I've circled the areas where the adders are in the image below. (There's two of them -- one for each pulse channel. The image in the tutorial is from the left one.)

 

Maybe the problem is only with the visualization itself. Everything makes sense from a boolean perspective if you assume polysilicon is "allowed to" pass over diffusion like that.

Poly can't cross diffusion without forming a device. It's possible that an identifier was used to prevent certain "gates" on ruby from forming actual gates, but that would have manifested itself on the die.

For manufacturing, poly crossing diffusion is used to synthesize source/drains of transistors. There is no "diffusion" under the gate (mostly). Below is a cross section of an NMOS transistor. Note that poly crossing diffusion was used to separate the source/drain diffusions. Synthesis to allow poly to cross diffusion without creating a device would have created source/drain regions that would not interact with a gate.


I don't know how sophisticated of a peel back methodology was employed. That design predated wholesale planarization...

 

I talked to the guy (Quietust) who put together Visual 2A03, which has the adder. As far as he understands it, the adders contain depletion-mode transistors that are always on. (They close only for negative voltage, and so remain open for both 0 V and 5 V.) Those are the transistors that aren't modeled, and where the poly is drawn underneath the diffusion. The depletion-mode transistors are "all used as pulldowns anyway", and so won't cause much of a problem. A special chemical stain would reveal the locations of the depletion implants, but that wasn't done for the 2A03.

He says he's pretty sure that it's a hack to save space, which also makes the chip harder to reverse-engineer. (Apparently the Z80 has depletion implants to make "fake" transistors that will cause the chip to malfunction if implemented as real transistors.)

The modeling was done starting with the assumption that those circuits must be adders (which is definitely correct) and then simply checking which transistors needed to "go away" for that to be true. The actual locations of the depletion-mode transistors is still speculative, as there are other possibilities with the same function.

 

The depletion-mode transistors are "all used as pulldowns anyway", and so won't cause much of a problem.

You mean pull-ups? And unnecessary pull-ups would reduce noise immunity...

In your highlighted adder net, resistors in the locations where poly is drawn "under" diffusion don't make sense. But, then, there could have been design limitations I'm not aware of.

BTW, how many metal layers did this process have? Did they still use buried contacts?

I worked with some interns at HP Labs who had made IC's by cutting "ruby". This was the late 70's when Computer Aided Design was starting to replace the old labor intensive methods; but the systems cost around half a million. I was doing layout for GHz speed SSI GaAs integrated circuits on an Applicon CAD system at the time. Back then, ECL was the fastest logic and could do about 300MHz...